/******************************************************************************/
/* */
/* Copyright (c) 1999 Sun Microsystems, Inc. All rights reserved. */
/* */
/* The contents of this file are subject to the current version of the Sun */
/* Community Source License, microSPARCII ("the License"). You may not use */
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/* */
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/* foreign patents, or pending applications. */
/* */
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/* registered trademarks of Sun Microsystems, Inc. in the United States and */
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/******************************************************************************/
/***************************************************************************
****************************************************************************
***
*** Program File: @(#)afx_slave.v
***
*** Description:
*** Implements the top level afx slave in the pcic for IIEP.
***
****************************************************************************
****************************************************************************/
`timescale 1ns/100ps
![[Up: pcic f_afx_slave]](v2html-up.gif)
module f_afx_slave
(
pcim_big_endian,
little_endian,
fast_gclk,
clock,
pci_clk,
pci_clk_sync,
pci_clk_sync_,
gclk_sync,
gclk_sync_,
reset,
// Configuration register signals
smbar0, // relocation reg 0,
smbar1, // relocation reg 1
sibar, // io relocation reg
msize0,
msize1,
pmbar0,
pmbar1,
pibar,
isize,
burst_enable, // mem write burst enable
prefetch_enable, // read prefetch enable
pci_config_wdata, // config reg data in
pci_config_wbe_l, // config reg byte marks
// add to support pci config accesses
pci_config_wbe, // config reg byte marks to config only
pci_config_wadd, // config reg write address
pci_config_radd, // config reg read address
pci_config_we, // config reg write enable
pci_config_rdata, // config reg read data
// add to support pci config writes
config_wbe, // config write byte enables from pci
config_add, //
config_data_in,
host_config_access_busy,
pci_config_access_busy,
config_write,
afx_mast_error_address,
afx_mast_error_cmd,
afx_mast_error,
sm_idle, // afx slave state machine idle
// AFX BUS signals
aen, // AFX address enable
ab, // AFX address bus
db, // AFX data bus (in only)
s_reply, // AFX s_reply
write_l, // AFX valid data, active low
lo_addr, // AFX 2nd address, active low
p_reply, // AFX p_reply
afx_slave_read_data, // afx slave read data for db
afx_slave_read_data_parity,
afx_slave_drive_db, // afx slave drive the data bus
// PCI core signals
pci_req, // PCI start core
pci_complete, // PCI core done (pci_clk)
pci_error, // PCI error (pci_clk)
pci_perror, // PCI parity error (pci_clk)
pci_async_perror, // PCI parity error (pci_clk)
pci_address, // PCI dma address
pci_wcount, // PCI dma word count
pci_command, // PCI command
pci_last, // PCI last dw data flag
pci_mast_fifo_write_lo, // PCI master fifo write
pci_mast_fifo_write_hi, // PCI master fifo write
pci_mast_xmit_fifo_flush,// PCI master xmit fifo flush
pci_mast_rcv_fifo_flush,// PCI master rcv fifo flush
pci_mast_rcv_fifo_empty_lo,// PCI master rcv fifo empty
pci_mast_rcv_fifo_empty_hi,// PCI master rcv fifo empty
pci_mast_rcv_fifo_read_lo,// read mas rcv lo word
pci_mast_rcv_fifo_read_hi,// read mas rcv lo word
pci_data_out, // PCI data from afx 64 bits
pci_bm_out_lo_l, // PCI byte mask from afx
pci_bm_out_hi_l, // PCI byte mask from afx
mas_rcv1_dataout, // PCI ls word read data
mas_rcv2_dataout, // PCI ms word read data
boot_mode, // host is in boot mode
bm_sel, // 2 bit boot sel field
mas_start_dma, // PCI core has started handshake
select_falcon_data // single gclk cycle pulse for read
// or write from afx bus
);
input pcim_big_endian;
input little_endian;
input reset;
input fast_gclk;
input clock;
input pci_clk;
input pci_clk_sync;
input pci_clk_sync_;
input gclk_sync;
input gclk_sync_;
input [3:0] smbar0;
input [3:0] smbar1;
input [3:0] sibar;
input [3:0] msize0;
input [3:0] msize1;
input [7:0] pmbar0;
input [7:0] pmbar1;
input [7:0] pibar;
input [3:0] isize;
input burst_enable;
input prefetch_enable;
input boot_mode;
wire boot_mode_hold;
input [1:0] bm_sel;
// bm_sel 00 = afx flash prom
// bm_sel 01 = afx flash prom ( 8 bit)
// bm_sel 10 = pci boot from cheerio f000.0000 to f0ff.ffff
// bm_sel 11 = pci boot from super io fffe.0000 to ffff.ffff
output [31:0] pci_config_wdata;
output [3:0] pci_config_wbe_l;
output [3:0] pci_config_wbe;
output [7:0] pci_config_wadd;
wire [7:0] pci_config_wadd;
wire [4:0] pci_config_wadd_ms;
wire [2:0] pci_config_wadd_ls;
assign pci_config_wadd = {pci_config_wadd_ms, pci_config_wadd_ls};
output [7:0] pci_config_radd;
wire [7:0] pci_config_radd;
wire [4:0] pci_config_radd_ms;
wire [2:0] pci_config_radd_ls;
assign pci_config_radd = {pci_config_radd_ms, pci_config_radd_ls};
output pci_config_we;
input [31:0] pci_config_rdata;
output [31:0] afx_mast_error_address;
wire [31:0] afx_mast_error_address;
output [3:0] afx_mast_error_cmd;
wire [3:0] afx_mast_error_cmd;
output afx_mast_error;
wire afx_mast_error;
// add for 2.0
input [3:0] config_wbe;
input [7:0] config_add;
input [31:0] config_data_in;
input pci_config_access_busy;
output host_config_access_busy;
input config_write;
input aen;
input [14:0] ab;
input [63:0] db;
input [1:0] s_reply;
input write_l;
input lo_addr;
output [1:0] p_reply;
output [63:0] afx_slave_read_data;
output [1:0] afx_slave_read_data_parity;
output afx_slave_drive_db;
output sm_idle;
output pci_req;
input pci_complete;
input pci_error;
input pci_perror;
input pci_async_perror;
output [31:0] pci_address;
output [7:0] pci_wcount;
output [3:0] pci_command;
output pci_last;
output pci_mast_fifo_write_lo;
output pci_mast_fifo_write_hi;
output pci_mast_xmit_fifo_flush;
output pci_mast_rcv_fifo_flush;
input pci_mast_rcv_fifo_empty_lo;
input pci_mast_rcv_fifo_empty_hi;
output pci_mast_rcv_fifo_read_lo;
output pci_mast_rcv_fifo_read_hi;
output select_falcon_data; // pulse for read or write.
output [63:0] pci_data_out; //
output [3:0] pci_bm_out_lo_l; //
output [3:0] pci_bm_out_hi_l; //
input [31:0] mas_rcv1_dataout;
input [31:0] mas_rcv2_dataout;
input mas_start_dma;
wire select_falcon_data;
wire [63:0] afx_slave_read_data;
wire [1:0] afx_slave_read_data_parity;
wire [27:3] pa_hold;
wire [3:0] bm_hold;
wire [31:3] pci_addr;
wire [63:0] afx_write_data;
wire [63:0] db;
wire [7:0] byte_mask;
wire [3:0] fifo_cmd_in;
wire [31:0] pci_address;
wire [7:0] pci_wcount;
wire [1:0] p_reply;
wire [3:0] cmd_out;
wire [3:0] next_cmd_out;
wire [28:0] addr_out;
wire [28:0] next_addr_out;
wire [3:0] pci_bm_out_lo_l;
wire [3:0] pci_bm_out_hi_l;
wire [3:0] fifo_bm_out;
wire [63:0] pci_data_out;
wire [2:0] cmd_fifo_full_count;
wire [2:0] data_fifo_full_count;
wire [31:0] configure_add;
wire [31:0] config_add_pci;
addr_reg addr_reg(
clock,
lo_addr,
aen,
ab,
s_reply,
reset,
p_reply,
pa_hold,
bm_hold,
afx_write,
load_addr_fifo,
load_bm_fifo,
load_cmd_fifo,
afx_slave_drive_db,
low_word_en,
boot_mode,
boot_mode_hold,
any_hi_word_en
);
addr_tlb addr_tlb(
pa_hold,
smbar0,
smbar1,
sibar,
msize0,
msize1,
pmbar0,
pmbar1,
pibar,
isize,
low_word_en,
any_hi_word_en,
config_add_31,
io_space_en,
mem_space_en,
config_add_en,
config_data_en,
falcon_reg_en,
special_cycle_en,
interrupt_ack_en,
boot_mode_hold,
bm_sel,
pci_addr
);
write_data write_data(
pcim_big_endian,
little_endian, // processor little endian
reset, //reset
clock, //fifo clock
db, //AFX data bus (big endian)
afx_write, //afx_write signal latched
write_l, //valid data on afx data bus, active lo
load_data_fifo, //load fifo to pci write data
afx_write_data); //data out
read_data read_data(
pcim_big_endian,
little_endian, //processor little endian
fifo_bm_out,
reset, //reset
clock, //clock
load_afx_read_data_lo, //
load_afx_read_data_hi, //
select_config_add, // selects config address for
select_falcon_data, // selects pci_config_rdata
// afx reads
select_error, // select all f's for error data
mas_rcv1_dataout, // ls word from pci
mas_rcv2_dataout, // ms word from pci
configure_add, // configuration address
pci_config_rdata, // configuration read data
afx_slave_read_data_parity,
afx_slave_read_data); //AFX data bus (big endian)
bm_decode bm_decode (
// add to support pci config operations
pci_config_access_busy,
config_wbe,
config_add[2:0],
pcim_big_endian,
fifo_bm_out,
pci_bm_out_lo_l,
pci_bm_out_hi_l,
pci_config_wadd_ls,
pci_config_radd_ls,
pci_config_wbe_l,
pci_config_wbe
) ;
cmd_map cmd_map(
afx_write, // afx write command
io_space_en, // io space decode
mem_space_en, // mem space decode
config_add_en, // configuration address decode
config_data_en, // configuration data decode
falcon_reg_en, // falcon registers decode
special_cycle_en, // special cycle decode
// except for decode of address reg
special_cycle_decode, // special cycle from config reg
interrupt_ack_en, // interrupt ack decode
boot_mode_hold, // boot mode
bm_sel, // boot mode select; non-zero is pci
fifo_cmd_in // encoded command
);
afx_slave_sm afx_slave_sm(
reset, // reset
fast_gclk, // fast gclk for p_reply timing
clock, // afx g clock
pci_clk, // pci clock
pci_clk_sync, // pci clock for sync cells
pci_clk_sync_, // pci clock for sync cells
gclk_sync, // gclk for sync cells
gclk_sync_, // gclk for sync cells
cmd_out, // afx fifo command
next_cmd_out, // afx fifo next command
addr_out, // afx fifo address
next_addr_out, // afx fifo next address
pci_bm_out_lo_l, // afx fifo bm out for bm, address 2:0, wc
pci_bm_out_hi_l, // afx fifo bm out for bm, address 2:0, wc
cmd_fifo_full_count, // afx command fifo full count
data_fifo_full_count, // afx data fifo full count
burst_enable, // burst enable from configuration
prefetch_enable, // mem read prefetch enable
config_add_pci, // configuration address
read_cmd_fifo, // read the afx command fifo
read_addr_fifo, // read the afx address fifo
read_bm_fifo, // read the afx byte mark fifo
read_data_fifo, // read the afx data fifo
sm_idle, // signal to enable power down when idle
pci_req, // start the pci core, must be synched to pci
pci_complete, // pci core complete must be synched back
// to clock
mas_start_dma,
pci_error, // pci core error, must be synched back
// to clock
pci_perror, // pci core error, must be synched back
pci_async_perror, // pci core error, must be synched back
// to clock
pci_address, // pci core starting address latched at pci_req
pci_wcount, // pci word count latched at pci_req
pci_command,
pci_last, // last xfer flag to pci core data fifo
pci_mast_fifo_write_lo, // write into pci master fifo
pci_mast_fifo_write_hi, // write into pci master fifo
pci_mast_xmit_fifo_flush,// flush pci core master xmit fifo (ERRORS)
pci_mast_rcv_fifo_flush,// flush pci core master rcv fifo
pci_mast_rcv_fifo_empty_lo, // receive fifo empty
pci_mast_rcv_fifo_empty_hi, // receive fifo empty
pci_mast_rcv_fifo_read_lo,// read mas rcv lo word
pci_mast_rcv_fifo_read_hi,// read mas rcv lo word
load_afx_read_data_lo,
load_afx_read_data_hi,
select_config_add,
select_error,
load_config_add,
select_falcon_data,
pci_config_we,
// add to support pci configuration writes
pci_config_access_busy,
host_config_access_busy,
config_write,
p_reply,
afx_mast_error_address, // error address to config
afx_mast_error_cmd, // error command to config
afx_mast_error // error to config
);
afx_slave_fifo afx_slave_fifo (
clock,
reset,
load_cmd_fifo, // load the command fifo
load_addr_fifo, // load address fifo from afx holding
load_bm_fifo, // load byte marks fifo from afx holding
load_data_fifo, // load data from afx holding
fifo_cmd_in, // command fifo data into fifo
pci_addr, // address in from afx holding
bm_hold, // byte marks in from afx
afx_write_data, // data in from afx holding
read_cmd_fifo, // read the command fifo to pci
read_addr_fifo, // read the address to pci
read_bm_fifo, // read the byte marks to pci
read_data_fifo, // read data to pci
cmd_out, // command out to pci
next_cmd_out, // command + 1 out to control logic
addr_out, // address out to pci
next_addr_out, // address + 1 out to control logic
fifo_bm_out, // byte marks out to bm_decoder
pci_data_out, // data out to pci
cmd_fifo_full_count, // command fifo full status to control
data_fifo_full_count, // data fifo full status to control
// add to support pci configuration operations
pci_config_access_busy,
config_add[7:3],
config_data_in,
pci_config_wdata,
pci_config_wadd_ms,
pci_config_radd_ms
);
config_addr config_addr(
reset, // reset
clock, // clock
pci_data_out[31:0], // data in -even word only!
load_config_add, // configuration address enable
special_cycle_decode, // special cycle decode
// converts config data writes to
// special cycle
config_add_31, // config_data control bit
configure_add, // config address for afx reads
config_add_pci); // config add to pci bus
endmodule
| This page: |
Created: | Thu Aug 19 12:00:50 1999 |
| From: |
../../../sparc_v8/ssparc/pcic/afx_slave/rtl/afx_slave.v
|