iotlb_cntl_wrt_d1 <= #1 1'b0;
      iotlb_cntl_wrt_d2 <= #1 1'b0;
      iotlb_cntl_wrt_d3 <= #1 1'b0;
      end
    else
      begin
      iotlb_cntl_wrt_d1 <= #1 iotlb_cntl_wrt;
      iotlb_cntl_wrt_d2 <= #1 iotlb_cntl_wrt_d1;
      iotlb_cntl_wrt_d3 <= #1 iotlb_cntl_wrt_d2;
      end
  end

assign xdma_addr[17:12] = (dma_sel_17_12) ? dma_addr[17:12] : iotlb_rd_out[17:12];
assign xdma_addr[23:18] = (dma_sel_23_18) ? dma_addr[23:18] : iotlb_rd_out[23:18];
assign xdma_addr[27:24] = (dma_sel_27_24) ? dma_addr[27:24] : iotlb_rd_out[27:24];

// iotlb_cd_in[3] == supervisor bit, always force on;
// assign iotlb_cd_in = (reset_l !== 1'b1 ) ? 42'h00000000008 :
//	(iotlb_rdwrt === 1'b1) ? {iotlb_cd_in_reg[3:2],iotlb_cd_in_reg[31:24],iotlb_cd_in_reg[1],iotlb_cd_in_reg[23:18],
//			iotlb_cd_in_reg[0],iotlb_cd_in_reg[17:12],18'h00008} : 
//	(xlate_start === 1'b1) ? {1'b1,1'b0,start_addr[31:24],1'b0,start_addr[23:18],1'b0,start_addr[17:12],18'h00008} :
//	(xlate_incr === 1'b1)  ? {1'b1,1'b0, next_addr[31:24],1'b0, next_addr[23:18],1'b0, next_addr[17:12],18'h00008} :
//		      {1'b1,1'b0,  dma_addr[31:24],1'b0,  dma_addr[23:18],1'b0,  dma_addr[17:12],18'h00008} ;

assign iotlb_cd_in = iotlb_mux_fun(reset_l, iotlb_rdwrt, xlate_start, xlate_incr, iotlb_valid_in, 
			iotlb_lvl3_in, iotlb_lvl2_in, iotlb_lvl1_in, 
			iotlb_cd_in_reg[31:12], start_addr[31:12], next_addr[31:12], dma_addr[31:12]) ; 


// Custom LSI tlb instance  
//--------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------

//IO_TLB io_tlb(
IOTLB io_tlb(
	.RD_OUT0(iotlb_rd_out[0]),
	.RD_OUT1(iotlb_rd_out[1]),
	.RD_OUT2(iotlb_rd_out[2]),
	.RD_OUT3(iotlb_rd_out[3]),
	.RD_OUT4(iotlb_rd_out[4]),
	.RD_OUT5(iotlb_rd_out[5]),
	.RD_OUT6(iotlb_rd_out[6]),
	.RD_OUT7(iotlb_rd_out[7]),
	.RD_OUT8(iotlb_rd_out[8]),
	.RD_OUT9(iotlb_rd_out[9]),
	.RD_OUT10(iotlb_rd_out[10]),
	.RD_OUT11(iotlb_rd_out[11]),
	.RD_OUT12(iotlb_rd_out[12]),
	.RD_OUT13(iotlb_rd_out[13]),
	.RD_OUT14(iotlb_rd_out[14]),
	.RD_OUT15(iotlb_rd_out[15]),
	.RD_OUT16(iotlb_rd_out[16]),
	.RD_OUT17(iotlb_rd_out[17]),
	.RD_OUT18(iotlb_rd_out[18]),
	.RD_OUT19(iotlb_rd_out[19]),
	.RD_OUT20(iotlb_rd_out[20]),
	.RD_OUT21(iotlb_rd_out[21]),
	.RD_OUT22(iotlb_rd_out[22]),
	.RD_OUT23(iotlb_rd_out[23]),
	.RD_OUT24(iotlb_rd_out[24]),
	.RD_OUT25(iotlb_rd_out[25]),
	.RD_OUT26(iotlb_rd_out[26]),
	.RD_OUT27(iotlb_rd_out[27]),

	.CD_OUT0(iotlb_cd_out[0]),
	.CD_OUT1(iotlb_cd_out[1]),
	.CD_OUT2(iotlb_cd_out[2]),
	.CD_OUT3(iotlb_cd_out[3]),
	.CD_OUT4(iotlb_cd_out[4]),
	.CD_OUT5(iotlb_cd_out[5]),
	.CD_OUT6(iotlb_cd_out[6]),
	.CD_OUT7(iotlb_cd_out[7]),
	.CD_OUT8(iotlb_cd_out[8]),
	.CD_OUT9(iotlb_cd_out[9]),
	.CD_OUT10(iotlb_cd_out[10]),
	.CD_OUT11(iotlb_cd_out[11]),
	.CD_OUT12(iotlb_cd_out[12]),
	.CD_OUT13(iotlb_cd_out[13]),
	.CD_OUT14(iotlb_cd_out[14]),
	.CD_OUT15(iotlb_cd_out[15]),
	.CD_OUT16(iotlb_cd_out[16]),
	.CD_OUT17(iotlb_cd_out[17]),
	.CD_OUT18(iotlb_cd_out[18]),
	.CD_OUT19(iotlb_cd_out[19]),
	.CD_OUT20(iotlb_cd_out[20]),
	.CD_OUT21(iotlb_cd_out[21]),
	.CD_OUT22(iotlb_cd_out[22]),
	.CD_OUT23(iotlb_cd_out[23]),
	.CD_OUT24(iotlb_cd_out[24]),
	.CD_OUT25(iotlb_cd_out[25]),
	.CD_OUT26(iotlb_cd_out[26]),
	.CD_OUT27(iotlb_cd_out[27]),
	.CD_OUT28(iotlb_cd_out[28]),
	.CD_OUT29(iotlb_cd_out[29]),
	.CD_OUT30(iotlb_cd_out[30]),
	.CD_OUT31(iotlb_cd_out[31]),
	.CD_OUT32(iotlb_cd_out[32]),
	.CD_OUT33(iotlb_cd_out[33]),
	.CD_OUT34(iotlb_cd_out[34]),
	.CD_OUT35(iotlb_cd_out[35]),
	.CD_OUT36(iotlb_cd_out[36]),
	.CD_OUT37(iotlb_cd_out[37]),
	.CD_OUT38(iotlb_cd_out[38]),
	.CD_OUT39(iotlb_cd_out[39]),
	.CD_OUT40(iotlb_cd_out[40]),
	.CD_OUT41(iotlb_cd_out[41]),

	.MISS ( iotlb_miss ),
	//.ACC_OK ( ),

	//.ERROR ( ),
	//.M_MISS ( ),
	//.SCN_OUT ( ),

	.RD_IN0(iotlb_rd_in[0]),
	.RD_IN1(iotlb_rd_in[1]),
	.RD_IN2(iotlb_rd_in[2]),
	.RD_IN3(iotlb_rd_in[3]),
	.RD_IN4(iotlb_rd_in[4]),
	.RD_IN5(iotlb_rd_in[5]),
	.RD_IN6(iotlb_rd_in[6]),
	.RD_IN7(iotlb_rd_in[7]),
	.RD_IN8(iotlb_rd_in[8]),
	.RD_IN9(iotlb_rd_in[9]),
	.RD_IN10(iotlb_rd_in[10]),
	.RD_IN11(iotlb_rd_in[11]),
	.RD_IN12(iotlb_rd_in[12]),
	.RD_IN13(iotlb_rd_in[13]),
	.RD_IN14(iotlb_rd_in[14]),
	.RD_IN15(iotlb_rd_in[15]),
	.RD_IN16(iotlb_rd_in[16]),
	.RD_IN17(iotlb_rd_in[17]),
	.RD_IN18(iotlb_rd_in[18]),
	.RD_IN19(iotlb_rd_in[19]),
	.RD_IN20(iotlb_rd_in[20]),
	.RD_IN21(iotlb_rd_in[21]),
	.RD_IN22(iotlb_rd_in[22]),
	.RD_IN23(iotlb_rd_in[23]),
	.RD_IN24(iotlb_rd_in[24]),
	.RD_IN25(iotlb_rd_in[25]),
	.RD_IN26(iotlb_rd_in[26]),
	.RD_IN27(iotlb_rd_in[27]),

	.CD_IN0(iotlb_cd_in[0]),
	.CD_IN1(iotlb_cd_in[1]),
	.CD_IN2(iotlb_cd_in[2]),
	.CD_IN3(iotlb_cd_in[3]),
	.CD_IN4(iotlb_cd_in[4]),
	.CD_IN5(iotlb_cd_in[5]),
	.CD_IN6(iotlb_cd_in[6]),
	.CD_IN7(iotlb_cd_in[7]),
	.CD_IN8(iotlb_cd_in[8]),
	.CD_IN9(iotlb_cd_in[9]),
	.CD_IN10(iotlb_cd_in[10]),
	.CD_IN11(iotlb_cd_in[11]),
	.CD_IN12(iotlb_cd_in[12]),
	.CD_IN13(iotlb_cd_in[13]),
	.CD_IN14(iotlb_cd_in[14]),
	.CD_IN15(iotlb_cd_in[15]),
	.CD_IN16(iotlb_cd_in[16]),
	.CD_IN17(iotlb_cd_in[17]),
	.CD_IN18(iotlb_cd_in[18]),
	.CD_IN19(iotlb_cd_in[19]),
	.CD_IN20(iotlb_cd_in[20]),
	.CD_IN21(iotlb_cd_in[21]),
	.CD_IN22(iotlb_cd_in[22]),
	.CD_IN23(iotlb_cd_in[23]),
	.CD_IN24(iotlb_cd_in[24]),
	.CD_IN25(iotlb_cd_in[25]),
	.CD_IN26(iotlb_cd_in[26]),
	.CD_IN27(iotlb_cd_in[27]),
	.CD_IN28(iotlb_cd_in[28]),
	.CD_IN29(iotlb_cd_in[29]),
	.CD_IN30(iotlb_cd_in[30]),
	.CD_IN31(iotlb_cd_in[31]),
	.CD_IN32(iotlb_cd_in[32]),
	.CD_IN33(iotlb_cd_in[33]),
	.CD_IN34(iotlb_cd_in[34]),
	.CD_IN35(iotlb_cd_in[35]),
	.CD_IN36(iotlb_cd_in[36]),
	.CD_IN37(iotlb_cd_in[37]),
	.CD_IN38(iotlb_cd_in[38]),
	.CD_IN39(iotlb_cd_in[39]),
	.CD_IN40(iotlb_cd_in[40]),
	.CD_IN41(iotlb_cd_in[41]),

	.FLUSH (iotlb_flush),
	.TLB_WE (iotlb_we),

	.ASEL (iotlb_asel),
	.ADDR0(iotlb_addr[0]),
	.ADDR1(iotlb_addr[1]),
	.ADDR2(iotlb_addr[2]),
	.ADDR3(iotlb_addr[3]),

	.CO_IN (1'b1),
	.CR (iotlb_cr),

	//.SCM (1'b0),
	//.SCN_IN (1'b0),
	//.TG_STROBE (1'b1),

	.CLK (gclk),
	//.PDM (standby_dsbl_tlb),
	.RST (~reset_l)
);


//--------------------------------------------------------------------------------------


//Generate ab_out and db_out of afx bus

reg [14:0] about_ff;
always @(posedge gclk) begin
      if (~reset_l)
          about_ff <= #1 15'b0;
      else if ((cadr_cyc & cas_cyc) | hold_cyc)
          about_ff <= #1 {xdma_addr[14:12],dma_addr[2],
			  xdma_addr[23],xdma_addr[21],dma_addr[11:3]};
      else if (radr_cyc | (cadr_cyc & ~cas_cyc))
          about_ff <= #1 {xdma_addr[27:25],xdma_addr[23],
			  xdma_addr[24],xdma_addr[22],xdma_addr[20:12]};
      else
          about_ff <= #1 about_ff;

end

wire [14:0] about =  about_ff ;

//wire aboe = ~am_gnt_l & ~am_gnt_l1;
//assign dboe = ~am_gnt_l & ~am_gnt_l1 & ~dma_read;

reg [1:0] aboe_ff;

assign oe_off = am_gnt_l & ~am_gnt_l1;

always @(posedge gclk) begin
    if (~reset_l | oe_off) begin
 	aboe_ff[1:0] <= #1 2'b0;
 	dboe_ff <= #1 1'b0;
    end
    else if (radr_cyc & ~am_gnt_l) begin
 	aboe_ff[1:0] <= #1 2'b11;
 	if (~dma_read)
 	   dboe_ff <= #1 1'b1;
    end
    else if (rmw & ~rmw_write & hold_cyc) begin
 	dboe_ff <= #1 1'b1;
    end
    else begin
 	aboe_ff[1:0] <= #1 aboe_ff[1:0];
 	dboe_ff <= #1 dboe_ff;
    end
end

assign aboe = aboe_ff[0];		//4 copies outgoing
assign aboe5  = aboe_ff[1];			//1 copy internal

assign dboe2_in = (~rmw & ~am_gnt_l & ~dma_read & ~oe_off & (radr_cyc|cadr_cyc|data_cyc|hold_cyc)) | 
		(rmw & ~oe_off & ((~rmw_write & hold_cyc) | rmw_write));   
						//dboe copy outgoing (before flop)



reg [63:0] dbout_ff;
reg dbpar1_ff, dbpar0_ff;
always @(posedge gclk) begin
    if (~reset_l) begin
  	dbout_ff <= #1 64'b0;
  	dbpar1_ff <= #1 1'b0;
  	dbpar0_ff <= #1 1'b0;
    end
    else if ((~dma_read|rmw)  & (radr_cyc1 | hold_cyc) & ~preempted) begin
  	dbout_ff <= #1 dma_data;
        //2.0: get rid of unnecessary nested begin/end
	//begin
	    //2.0: fix to 1.0 bug on dma_parity
	    //dbpar1_ff <= #1 (dma_data[63:56]^dma_data[55:48]^dma_data[47:40]^dma_data[39:32]);
	    //dbpar0_ff <= #1 (dma_data[31:24]^dma_data[23:16]^dma_data[15:8]^dma_data[7:0]);
	    dbpar0_ff <= #1 ^({dma_data[63:32],mm_oddpar});
	    dbpar1_ff <= #1 ^({dma_data[31:0],mm_oddpar});
	//end
    end
    else
	dbout_ff <=  dbout_ff ;
end
//convert from little to big endian, data must be swapped even in big
// endian to make sure memory addresses match
wire [63:0] dbout = {dbout_ff[7:0],dbout_ff[15:8],
		     dbout_ff[23:16],dbout_ff[31:24],
		     dbout_ff[39:32],dbout_ff[47:40],
		     dbout_ff[55:48],dbout_ff[63:56]};
//memory parity (already adjusted for endianness)
wire [1:0] mparout = {dbpar1_ff,dbpar0_ff};

//synopsys translate_off
reg [31:0] afx_addr_shifted;
reg [31:0] afx_addr_unshifted;
always @(negedge valid_l) begin
     afx_addr_unshifted <= #1 dma_addr;
     afx_addr_shifted <= #1 {2'b00,dma_addr[31:2]};
end

always @(posedge data_cyc) begin
   if (rmw & ~rmw_write)
     $display("AFXM: doing DMA rmw...");
end

always @(posedge gclk) begin
   if (~valid_l & dma_read)
     $display("AFXM: DMA read %h_%h @ %h (%h), wm=%b,count=%h", 
		dbin[63:32],dbin[31:0],afx_addr_shifted,afx_addr_unshifted, am_wm,xfer_count);
   else if (~valid_l & ~dma_read)
     $display("AFXM: DMA write %h_%h @ %h (%h), wm=%b, count=%h", 
		dbout[63:32],dbout[31:0],afx_addr_shifted,afx_addr_unshifted,am_wm,xfer_count);
end

always @(posedge preempted) begin
     $display("AFXM:DMA xfer preempted: %h @ %h (%h)",dma_data,afx_addr_shifted, afx_addr_unshifted);
end

//synopsys translate_on

//AFX MASTER STATE MACHINE
	afxm_sm afxm_sm1(
        .am_cstb_l      (am_cstb_l),    // afx req from falcon
        .dma_burst      (dma_burst),   	// dma r/w burst indicator
        .cross_page     (cross_page),   // page cross flag during burst
        .idle_cyc       (idle_cyc),     // afxm_sm idle state
        .req_cyc        (req_cyc),      // afxm_sm cstb_l request state
        .radr_cyc       (radr_cyc),     // afxm_sm row_address state
        .radr_cyc1      (radr_cyc1),    // afxm_sm delayed row_address state
        .rcv_fifo_read  (rcv_fifo_read),  //tar_rcv1_fifo_read, tar_rcv2_fifo_read
        .cadr_cyc       (cadr_cyc),     // afxm_sm column_address state
        .cadr_cyc1      (cadr_cyc1),    // afxm_sm delayed column_address state
        .data_cyc       (data_cyc),     // afxm_sm data valid state
        .data_cyc1      (data_cyc1),    // afxm_sm delayed data valid state
        .hold_cyc       (hold_cyc),     // afxm_sm hold_address state
        .hold_cyc1      (hold_cyc1),    // afxm_sm delayed hold_address state
        .preempted      (preempted),    // data xfer preempted flag
        .error          (error),        // afxm_sm error state
        .rmw_write      (rmw_write),    // write/~read cycle of rmw
        .clk            (gclk),         // clock @ 1/3 cpu clock
        .valid_l        (valid_l), // read/write select
        .cas_cyc        (cas_cyc),      // low address select
        .am_gnt_l       (am_gnt_l),     // afx grant to falcon
        .activity       (~afxm_idle),   // start indicator to afxm_sm
        .rcv_fifo_empty (rcv_fifo_empty_g),    // write fifos empty indicator
        .xfer_count      (xfer_count),    // data transfer count
        .abort_write    (abort_write),  // abort burst write 
        .pend_abort_write (pend_abort_write),  // pending abort burst write 
        .no_rcv_read    (no_rcv_read),  // no valid write data due to empty
        .delayed_abort_write (delayed_abort_write),  // abort due to last_single
        .rmw       	(rmw),    	// current sub-word write (rd-mod-wrt)
        .rmw_next      	(rmw_next),    	// next sub-word write (rd-mod-wrt)
        .am_read        (am_read),	// r/w indicator for IIe
        .dma_read       (dma_read),	// dma r/w indicator for Falcon
        .trcv_val       (trcv_val),	// tar_rcv_fifo dataout valid
        .cmd_start_g    (cmd_start_g),	// pci target busy
        .txmt_stop_fifo_wr_g (txmt_stop_fifo_wr_g),	// stop xmit_fifo writes (from pci_slave)
        //.pack_done      (pack_done),	// tar_rcv_fifo packing done
	.reset_l        (reset_l)    	// system or PCI reset_l
        );


// old word_mask.v file
/* This function maps the allowable patterns of the 8 pci byte enable bits 
   to a 2-bit afx word mask.  Only 64-bit and 32-bit DRAM writes are
   allowed without having to do a read-modify-write.  For the non-allowable
   patterns, a read-modify-write will be have to be performed by Falcon,
   using the 8 pci be's to mask any combination of the 8 byte lanes.
*/

function [1:0] wm_encode;
   input [7:0] pci_be;
   reg [1:0] wm;
begin
    case (pci_be)
	//double-word (64-bit) DRAM write:
    	8'b00000000: 	begin				// le:76543210
		            wm = 2'b11;			// be:01234567
	    	      	end
	//odd-word (32-bit) DRAM write:
    	8'b00001111: 	begin				// le:7654----
		            wm = 2'b01;			// be:----4567
	    	      	end
	//even-word (32-bit) DRAM write:
    	8'b11110000: 	begin				// le:----3210
		            wm = 2'b10;			// be:0123----
	    	      	end
	//all other be patterns require rmw (read-modify-write):
    	default: 	begin			
		            wm = 2'b00;			// reserved pattern
	    	      	end
    endcase
    wm_encode = wm;

end

endfunction

function [41:0] iotlb_mux_fun ;
input		reset_l;
input		iotlb_rdwrt;
input		xlate_start;
input		xlate_incr;
input		iotlb_valid_in;
input		iotlb_lvl3_in;
input		iotlb_lvl2_in;
input		iotlb_lvl1_in;
input	[31:12]	iotlb_cd_in_reg, start_addr, next_addr, dma_addr ; 
reg	[41:0]	tmp_mux_in ;
begin
  casex ({reset_l,iotlb_rdwrt,xlate_start,xlate_incr})
	4'b0xxx:	tmp_mux_in = 42'h00000000008;
	4'b11xx:	tmp_mux_in = {iotlb_valid_in,iotlb_lvl1_in,iotlb_cd_in_reg[31:24],
					iotlb_lvl2_in,iotlb_cd_in_reg[23:18],
					iotlb_lvl3_in,iotlb_cd_in_reg[17:12],18'h00008};
	4'b101x:	tmp_mux_in = {1'b1,1'b0,start_addr[31:24],1'b0,start_addr[23:18],
					1'b0,start_addr[17:12],18'h00008};
	4'b1001:	tmp_mux_in = {1'b1,1'b0, next_addr[31:24],1'b0, next_addr[23:18],
					1'b0, next_addr[17:12],18'h00008}; 
	4'b1000:	tmp_mux_in = {1'b1,1'b0, dma_addr[31:24],1'b0, dma_addr[23:18],
					1'b0, dma_addr[17:12],18'h00008}; 
	default: tmp_mux_in = {1'b1,1'b0, dma_addr[31:24],1'b0, dma_addr[23:18], 
				1'b0, dma_addr[17:12],18'h00008};
  endcase
iotlb_mux_fun = tmp_mux_in ;
end
endfunction

// Added spare cells 
 
        spares  afxm_spares ();
 
endmodule