/******************************************************************************/
/* */
/* Copyright (c) 1999 Sun Microsystems, Inc. All rights reserved. */
/* */
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/******************************************************************************/
// @(#)areginexactslice.v 1.1 4/7/92
//
module AregInexactSlice
(AM, notAM31_3, notAM2_0);
input [31:0] AM
;
output notAM31_3
, notAM2_0
;
wire [11:4] notAORed
;
ME_NOR3 aig0 (AM[0], AM[1], AM[2], notAM2_0);
ME_NOR2 aig5 (AM[30], AM[31], notAORed[11]);
ME_NOR3 aig6 (AM[27], AM[28], AM[29], notAORed[10]);
ME_NOR4 ai54 (AM[25], AM[26], AM[23], AM[24], notAORed[9]);
ME_NOR4 ai44 (AM[21], AM[22], AM[19], AM[20], notAORed[8]);
ME_NOR4 ai34 (AM[17], AM[18], AM[15], AM[16], notAORed[7]);
ME_NOR4 ai24 (AM[13], AM[14], AM[11], AM[12], notAORed[6]);
ME_NOR4 ai14 (AM[9], AM[10], AM[7], AM[8], notAORed[5]);
ME_NOR4 ai04 (AM[5], AM[6], AM[3], AM[4], notAORed[4]);
ME_NAND4 ai27 (notAORed[8], notAORed[9], notAORed[10], notAORed[11], AM31_19
);
ME_NAND4 ai17 (notAORed[4], notAORed[5], notAORed[6], notAORed[7], AM18_3
);
ME_NOR2 aizz (AM31_19, AM18_3, notAM31_3);
endmodule
This page: |
Created: | Thu Aug 19 12:02:39 1999 |
| From: |
../../../sparc_v8/ssparc/fpu/fp_frac/rtl/areginexactslice.v
|