/******************************************************************************/
/* */
/* Copyright (c) 1999 Sun Microsystems, Inc. All rights reserved. */
/* */
/* The contents of this file are subject to the current version of the Sun */
/* Community Source License, microSPARCII ("the License"). You may not use */
/* this file except in compliance with the License. You may obtain a copy */
/* of the License by searching for "Sun Community Source License" on the */
/* World Wide Web at http://www.sun.com. See the License for the rights, */
/* obligations, and limitations governing use of the contents of this file. */
/* */
/* Sun Microsystems, Inc. has intellectual property rights relating to the */
/* technology embodied in these files. In particular, and without limitation, */
/* these intellectual property rights may include one or more U.S. patents, */
/* foreign patents, or pending applications. */
/* */
/* Sun, Sun Microsystems, the Sun logo, all Sun-based trademarks and logos, */
/* Solaris, Java and all Java-based trademarks and logos are trademarks or */
/* registered trademarks of Sun Microsystems, Inc. in the United States and */
/* other countries. microSPARC is a trademark or registered trademark of */
/* SPARC International, Inc. All SPARC trademarks are used under license and */
/* are trademarks or registered trademarks of SPARC International, Inc. in */
/* the United States and other countries. Products bearing SPARC trademarks */
/* are based upon an architecture developed by Sun Microsystems, Inc. */
/* */
/******************************************************************************/
/***************************************************************************
****************************************************************************
***
*** Program File: @(#)me_cells.v
***
****************************************************************************
****************************************************************************/
/*
PRIMATIVES
Latches
Combinational logic gates
Multiplexors
Pads
Clock buffers
MACROS -- use seperate file macros.v
Registers
Wide multiplexors
Bus drivers
Shifters
Alus
Adders
Rams
Roms
*/
/* Latches
ME_LD1 simple d latch, active LOW clock
ME_FD1 fimple ff active on positive clock edge
ME_FD1E FD2 with a data load enable
ME_FD1E2 FD2 with two data inputs, each with is own enable.
FJK1 JK flip flop, pos edge load.
FJK2 JK flip flop, pos edge load, with active low clear.
*/
/* logic Gates
NAND{n} n input nand gate
NOR{n} n input nor gate
AND{n} n input and gate
OR{n} n input or gate
ME_INVA invertor
ME_BUFF buffer
ME_DELBUFF buffer with approx 3ns delay
ME_TSBUFF tristate buffer
ME_XOR2 2 input xor gate
ME_XNOR2 2 input xnor
ME_ADD2 half adder
ME_ADD3 full adder
*/
/* Matrix Gates
ME_AnOmI And-Or-Invert gates
ME_OnAmI Or-And-Invert gates
*/
/* Multiplexors/selectors
MUX{n} n input multiplexor with seperate selectors
NMUX{n} n input inverting multiplexor with seperate selectors
MUX{n)B binary coded selectors.
NMUX{n)B binary coded selectors, inverting
ME_NMUX2BA as NMUX2B except you must supply true and false of control inputs
*/
/* Pads */
/* MACROS */
/* registers
DREG_{x}_{y} x bit wide register with y inputs. transparent when clock high
FREG_{x}_{y} x bit wide register with y inputs. edge trigger on posedge strobe
MUX_{x}_{y} x bit wide multiplexor with y inputs
*/
/* function blocks
ALU_{x} x bit wide ALU
ME_ADD_{x} x bit wide add/subtract
*/
/* roms and roms
ME_ROM_{x}_{y} x bit wide rom with y address bits
ME_RAM_{x}_{y} x bit wide ram with y address bits
ME_RAM3_{x}_{y} x bit wide 3 port ram with y address bits
*/
/* Actual modules */
![[Up: DecodeCmpAndNeg dcep4]](v2html-up.gif)
![[Up: DecodeCmpAndNeg dcep5]](v2html-up.gif)
![[Up: DecodeCmpAndNeg iggypop]](v2html-up.gif)
![[Up: FDREG_1Byte f0]](v2html-up.gif)
![[Up: FDREG_1Byte f1]](v2html-up.gif)
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![[Up: FDREG_1Byte f7]](v2html-up.gif)
![[Up: sticky s28_reg]](v2html-up.gif)
![[Up: sticky s51_reg]](v2html-up.gif)
![[Up: carry51 carry28Reg]](v2html-up.gif)
![[Up: carry51 carry51Reg]](v2html-up.gif)
![[Up: MicrocodeRom scanloadrom_ff]](v2html-up.gif)
![[Up: RoundModeLogic rm0f]](v2html-up.gif)
![[Up: RoundModeLogic rm1f]](v2html-up.gif)
![[Up: SignLogic bsf]](v2html-up.gif)
![[Up: fpm_frac rgstrX1]](v2html-up.gif)
![[Up: fpm_frac rgstrX2]](v2html-up.gif)
![[Up: fpm_frac rgstrX3]](v2html-up.gif)
![[Up: ExpShifter err]](v2html-up.gif)
![[Up: ShiftDec ma1]](v2html-up.gif)
![[Up: ShiftDec ma0]](v2html-up.gif)
![[Up: NullExcepLogic rf]](v2html-up.gif)
![[Up: NullExcepLogic zrd]](v2html-up.gif)
![[Up: SampleReset rs]](v2html-up.gif)
![[Up: SampleReset rva]](v2html-up.gif)
![[Up: FDREG_1Bit f0]](v2html-up.gif)
![[Up: MIptrMultiplexor mib0]](v2html-up.gif)
... (truncated)
module ME_FD1
(cp, d, q, qn);
input d
, cp
;
output q
, qn
;
// N1Z000 gnd(GND);
// ASFFA dff (.Q(q), .XQ(qn), .D(d), .SM(GND), .SI(GND), .CK(cp));
Mflipflop_noop dff (.out(q), .in(d), .clock(cp) );
assign qn = ~q;
endmodule
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module ME_FD1_B
(cp, d, q, qn);
input d
, cp
;
output q
, qn
;
// N1Z000 gnd(GND);
// ASFFA dff (.Q(q), .XQ(qn), .D(d), .SM(GND), .SI(GND), .CK(cp));
Mflipflop_noop dff (.out(q), .in(d), .clock(cp) );
assign qn = ~q;
endmodule
![[Up: rfrw_ctl sgl1_ff]](v2html-up.gif)
![[Up: rfrw_ctl sgl2_ff]](v2html-up.gif)
![[Up: rfrw_ctl byp1_lo_ff]](v2html-up.gif)
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![[Up: qcore_ctl fpp_ld_ff]](v2html-up.gif)
![[Up: qcore_ctl fpm_abort_ff]](v2html-up.gif)
![[Up: ME_FD1P2 f0]](v2html-up.gif)
![[Up: ME_FD1P2 f1]](v2html-up.gif)
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![[Up: fhold_ctl fhold_perf1_ff]](v2html-up.gif)
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![[Up: stat_ctl exemode_one_ff]](v2html-up.gif)
![[Up: stat_ctl exemode_two_ff]](v2html-up.gif)
![[Up: ME_FD1P_6 f0]](v2html-up.gif)
![[Up: ME_FD1P_6 f1]](v2html-up.gif)
![[Up: ME_FD1P_6 f2]](v2html-up.gif)
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![[Up: ME_FD1P_6 f5]](v2html-up.gif)
module ME_FD1P
(cp, d, q, qn); // should be a high drive version of ME_FD1;
input d
, cp
; // for simulation, they are the same.
output q
, qn
;
// N1Z000 gnd(GND);
// ASFFA dff (.Q(q), .XQ(qn), .D(d), .SM(GND), .SI(GND), .CK(cp));
Mflipflop_noop dff (.out(q), .in(d), .clock(cp) );
assign qn = ~q;
endmodule
![[Up: qcore_ctl fmul_e_ff]](v2html-up.gif)
![[Up: qcore_ctl qne_0_ff]](v2html-up.gif)
![[Up: qcore_ctl qne_1_ff]](v2html-up.gif)
![[Up: qcore_ctl qne_2_ff]](v2html-up.gif)
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![[Up: qcore_ctl fq_unimp_0_ff]](v2html-up.gif)
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![[Up: qcore_ctl fq_rd_dbl_0_ff]](v2html-up.gif)
![[Up: qcore_ctl fq_rd_dbl_1_ff]](v2html-up.gif)
![[Up: qcore_ctl fq_rd_dbl_2_ff]](v2html-up.gif)
![[Up: qcore_ctl fq_start_0_ff]](v2html-up.gif)
![[Up: qcore_ctl fq_start_1_ff]](v2html-up.gif)
![[Up: qcore_ctl fq_start_2_ff]](v2html-up.gif)
![[Up: qcore_ctl fpm_res_ff]](v2html-up.gif)
![[Up: fhold_ctl finst_e_ff]](v2html-up.gif)
![[Up: fhold_ctl fop_e_ff]](v2html-up.gif)
![[Up: fhold_ctl ldreg_e_ff]](v2html-up.gif)
![[Up: fhold_ctl ldreg_w_ff]](v2html-up.gif)
![[Up: fhold_ctl rs1dbl_e_ff]](v2html-up.gif)
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![[Up: fhold_ctl rddbl_e_ff]](v2html-up.gif)
![[Up: fhold_ctl rdused_e_ff]](v2html-up.gif)
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![[Up: stat_ctl finst_ff_e]](v2html-up.gif)
![[Up: stat_ctl finst_ff_w]](v2html-up.gif)
... (truncated)
module ME_FDS2LP
(d, cp, cr, ld, q, qn);
// ld is active high, cr is active low
input d
, cp
, cr
, ld
;
output q
, qn
;
// N1Z000 gnd(GND);
// wire hold;
// JINVA i0 ( .O(hold), .A(ld) );
// ASFFRHA dff ( .Q(q), .XQ(qn), .D(d), .SM(GND), .SI(GND),
// .H(hold), .R(cr), .CK(cp) ) ;
wire load_l
;
assign load_l = ~ld;
Mflipflop_rh dff (.out(q), .in(d), .enable_l(load_l), .reset_l(cr), .clock(cp));
assign qn = ~q;
endmodule
![[Up: FREG_1Bit f0]](v2html-up.gif)
![[Up: FREG_5bit f0]](v2html-up.gif)
![[Up: FREG_S_5bit f0]](v2html-up.gif)
![[Up: fpm_frac dblReg]](v2html-up.gif)
![[Up: fpm_frac inxReg]](v2html-up.gif)
![[Up: FREG_1Byte f0]](v2html-up.gif)
![[Up: FREG_1Byte f1]](v2html-up.gif)
![[Up: FREG_1Byte f2]](v2html-up.gif)
![[Up: FREG_1Byte f3]](v2html-up.gif)
![[Up: FREG_1Byte f4]](v2html-up.gif)
![[Up: FREG_1Byte f5]](v2html-up.gif)
![[Up: FREG_1Byte f6]](v2html-up.gif)
![[Up: FREG_1Byte f7]](v2html-up.gif)
![[Up: sign signX2Reg]](v2html-up.gif)
![[Up: FREG_2bit f0]](v2html-up.gif)
![[Up: FREG_4Bit f0]](v2html-up.gif)
![[Up: FREG_S_4Bit f0]](v2html-up.gif)
![[Up: ImplementedCheck ggh1]](v2html-up.gif)
![[Up: ImplementedCheck ni]](v2html-up.gif)
![[Up: FREG_8bit f0]](v2html-up.gif)
module ME_FD1E
(cp, te, d, q, qn);
// like FD1 but with enable
// note enable is active high
input d
, cp
, te
;
output q
, qn
;
// N1Z000 gnd(GND);
// wire hold;
// JINVA i0 ( .O(hold), .A(te) );
// ASFFHA dff ( .Q(q), .XQ(qn), .D(d), .SM(GND), .SI(GND),
// .H(hold), .CK(cp)) ;
wire load_l
;
assign load_l = ~te;
Mflipflop dff (.out(q), .in(d), .clock(cp), .enable_l(load_l));
assign qn = ~q;
endmodule
![[Up: FREG_8bit_s f0]](v2html-up.gif)
![[Up: FREG_8bit_s f1]](v2html-up.gif)
![[Up: MicrocodeRom romor540]](v2html-up.gif)
![[Up: MicrocodeRom romor551]](v2html-up.gif)
![[Up: MicrocodeRom romor542]](v2html-up.gif)
![[Up: MicrocodeRom romor553]](v2html-up.gif)
![[Up: MicrocodeRom romor554]](v2html-up.gif)
![[Up: MicrocodeRom romor555]](v2html-up.gif)
![[Up: MicrocodeRom romor556]](v2html-up.gif)
module ME_FD1E_B
(cp, te, d, q, qn);
// like FD1 but with enable
// note enable is active high
input d
, cp
, te
;
output q
, qn
;
// N1Z000 gnd(GND);
// wire hold;
// JINVA i0 ( .O(hold), .A(te) );
// ASFFHA dff ( .Q(q), .XQ(qn), .D(d), .SM(GND), .SI(GND),
// .H(hold), .CK(cp)) ;
wire load_l
;
assign load_l = ~te;
Mflipflop dff (.out(q), .in(d), .clock(cp), .enable_l(load_l));
assign qn = ~q;
endmodule
![[Up: rfrw_ctl cuthold]](v2html-up.gif)
![[Up: qcore_ctl fpm_st_ff]](v2html-up.gif)
![[Up: qcore_ctl fpm_x1_ff]](v2html-up.gif)
![[Up: qcore_ctl fpm_x2_ff]](v2html-up.gif)
![[Up: qcore_ctl fpm_x3_ff]](v2html-up.gif)
![[Up: fhold_ctl held_stdfq_ff]](v2html-up.gif)
![[Up: fhold_ctl fhold_ff]](v2html-up.gif)
![[Up: stat_ctl exemode_ff]](v2html-up.gif)
![[Up: stat_ctl penmode_ff]](v2html-up.gif)
![[Up: stat_ctl excmode_ff]](v2html-up.gif)
module ME_FD1R
(d, cp, cr, q, qn);
// CR (reset) is active low
input d
, cp
, cr
;
output q
, qn
;
// N1Z000 gnd(GND);
// ASFFRA dff ( .Q(q), .XQ(qn), .D(d), .SM(GND), .SI(GND),
// .R(cr), .CK(cp) ) ;
Mflipflop_r dff (.out(q), .in(d), .reset_l(cr), .clock(cp));
assign qn = ~q;
endmodule
// Logic Gates
![[Up: acell10 g30]](v2html-up.gif)
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![[Up: FREG_8bit_s i0]](v2html-up.gif)
![[Up: FREG_8bit_s i1]](v2html-up.gif)
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![[Up: SignLogic sblc]](v2html-up.gif)
![[Up: SignLogic sbe2]](v2html-up.gif)
... (truncated)
module ME_INV_A
(a, x); // Meanest gate
input a
;
output x
;
JINVA i (.O(x), .A(a) );
endmodule
![[Up: DecodeCmpAndNeg dcep1]](v2html-up.gif)
![[Up: DecodeCmpAndNeg dcep9]](v2html-up.gif)
![[Up: DecodeCmpAndNeg dcep6]](v2html-up.gif)
![[Up: ExpConstantCtl z05]](v2html-up.gif)
![[Up: CondMux h_1]](v2html-up.gif)
![[Up: CondMux vc_2]](v2html-up.gif)
![[Up: StickyPairNC g27]](v2html-up.gif)
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![[Up: acell4 g15]](v2html-up.gif)
![[Up: RoundModeLogic cmpbits]](v2html-up.gif)
![[Up: ME_MUX_2B_11 i0]](v2html-up.gif)
![[Up: ExpShifter g33]](v2html-up.gif)
![[Up: fp_frac ifs]](v2html-up.gif)
![[Up: NullExcepLogic g_0]](v2html-up.gif)
![[Up: NullExcepLogic yyc]](v2html-up.gif)
![[Up: NullExcepLogic yye]](v2html-up.gif)
![[Up: StickyPairNCI g31]](v2html-up.gif)
![[Up: StickyPairNCI g27]](v2html-up.gif)
![[Up: adder13 s1]](v2html-up.gif)
![[Up: ShiftRightCtl g86]](v2html-up.gif)
![[Up: ShiftRightCtl g89]](v2html-up.gif)
![[Up: ShiftRightCtl g90]](v2html-up.gif)
![[Up: YMuxCtl i00]](v2html-up.gif)
![[Up: YMuxCtl i10]](v2html-up.gif)
![[Up: AregLoadCtl iopl]](v2html-up.gif)
![[Up: AregLoadCtl alcn7]](v2html-up.gif)
![[Up: AregLoadCtl alcn8]](v2html-up.gif)
![[Up: ExpRegLoadCtl iopl]](v2html-up.gif)
![[Up: stat_ctl g0]](v2html-up.gif)
![[Up: stat_ctl g1]](v2html-up.gif)
... (truncated)
module ME_INVA
(a, x);
input a
;
output x
;
JINVA i (.O(x), .A(a) );
endmodule
![[Up: ME_FREGA_1_52 m20]](v2html-up.gif)
![[Up: ME_FREGA_1_54 m20]](v2html-up.gif)
![[Up: ME_FREGA_1_58 m20]](v2html-up.gif)
![[Up: ME_FREGA_1_64 m20]](v2html-up.gif)
![[Up: EntryCheck i_0]](v2html-up.gif)
![[Up: EntryCheck i_1]](v2html-up.gif)
![[Up: EntryCheck i_2]](v2html-up.gif)
![[Up: EntryCheck i_3]](v2html-up.gif)
![[Up: EntryCheck i_4]](v2html-up.gif)
![[Up: EntryCheck i_5]](v2html-up.gif)
![[Up: EntryCheck i_6]](v2html-up.gif)
![[Up: EntryCheck i_7]](v2html-up.gif)
![[Up: acell10 g15]](v2html-up.gif)
![[Up: acell16 g15]](v2html-up.gif)
![[Up: SignDp rlokout]](v2html-up.gif)
![[Up: ME_FREGA_5_58 ie1]](v2html-up.gif)
![[Up: ME_FREGA_5_58 ia0]](v2html-up.gif)
![[Up: ME_FREGA_5_58 ib0]](v2html-up.gif)
![[Up: ME_FREGA_5_58 ic0]](v2html-up.gif)
![[Up: ME_NMUX_2B_57 g10]](v2html-up.gif)
![[Up: ME_NMUX_2B_58 g10]](v2html-up.gif)
![[Up: FREG_5bit b0]](v2html-up.gif)
![[Up: FREG_8bit_s b0]](v2html-up.gif)
![[Up: FREG_S_5bit b0]](v2html-up.gif)
![[Up: ME_MUX_2B_13 g12]](v2html-up.gif)
![[Up: ME_MUX_2B_32 g10]](v2html-up.gif)
![[Up: ME_MUX_2B_B_13 g12]](v2html-up.gif)
![[Up: ExpShifter g19]](v2html-up.gif)
![[Up: ME_MUX_2B_52 g10]](v2html-up.gif)
![[Up: ME_MUX_2B_58 g10]](v2html-up.gif)
![[Up: ME_MUX_2B_B_58 g10]](v2html-up.gif)
... (truncated)
module ME_INV_B
(a, x);
input a
;
output x
;
JINVB i (.O(x), .A(a) );
endmodule
![[Up: ME_FREGA_1_52 m21]](v2html-up.gif)
![[Up: ME_FREGA_1_52 m22]](v2html-up.gif)
![[Up: ME_FREGA_1_54 m21]](v2html-up.gif)
![[Up: ME_FREGA_1_54 m22]](v2html-up.gif)
![[Up: ME_FREGA_1_58 m21]](v2html-up.gif)
![[Up: ME_FREGA_1_58 m22]](v2html-up.gif)
![[Up: ME_FREGA_1_64 m21]](v2html-up.gif)
![[Up: ME_FREGA_1_64 m22]](v2html-up.gif)
![[Up: ME_FREGA_5_58 ie2]](v2html-up.gif)
![[Up: ME_FREGA_5_58 ie3]](v2html-up.gif)
![[Up: ME_FREGA_5_58 ia1]](v2html-up.gif)
![[Up: ME_FREGA_5_58 ia2]](v2html-up.gif)
![[Up: ME_FREGA_5_58 ia3]](v2html-up.gif)
![[Up: ME_FREGA_5_58 ib1]](v2html-up.gif)
![[Up: ME_FREGA_5_58 ib2]](v2html-up.gif)
![[Up: ME_FREGA_5_58 ic1]](v2html-up.gif)
![[Up: ME_FREGA_5_58 ic2]](v2html-up.gif)
![[Up: ME_NMUX_2B_57 g11]](v2html-up.gif)
![[Up: ME_NMUX_2B_57 g12]](v2html-up.gif)
![[Up: ME_NMUX_2B_57 g13]](v2html-up.gif)
![[Up: ME_NMUX_2B_57 g14]](v2html-up.gif)
![[Up: ME_NMUX_2B_58 g11]](v2html-up.gif)
![[Up: ME_NMUX_2B_58 g12]](v2html-up.gif)
![[Up: ME_NMUX_2B_58 g13]](v2html-up.gif)
![[Up: ME_NMUX_2B_58 g14]](v2html-up.gif)
![[Up: ME_MUX_2B_32 g11]](v2html-up.gif)
![[Up: ME_MUX_2B_32 g12]](v2html-up.gif)
![[Up: ME_MUX_2B_52 g11]](v2html-up.gif)
![[Up: ME_MUX_2B_52 g12]](v2html-up.gif)
![[Up: ME_MUX_2B_58 g11]](v2html-up.gif)
![[Up: ME_MUX_2B_58 g12]](v2html-up.gif)
... (truncated)
module ME_INV_C
(a, x);
input a
;
output x
;
JINVC i (.O(x), .A(a) );
endmodule
![[Up: SignDp rvo4]](v2html-up.gif)
![[Up: ME_YmuxSlice b1]](v2html-up.gif)
![[Up: ME_YmuxSlice b2]](v2html-up.gif)
![[Up: ME_YmuxSlice b3]](v2html-up.gif)
![[Up: ME_YmuxSlice b7]](v2html-up.gif)
![[Up: ME_YmuxSlice b8]](v2html-up.gif)
module ME_INV_D
(a, x);
input a
;
output x
;
JINVD i (.O(x), .A(a) );
endmodule
![[Up: ME_INV_A_58 h0]](v2html-up.gif)
![[Up: ME_INV_A_58 h2]](v2html-up.gif)
![[Up: ME_INV_A_58 h3]](v2html-up.gif)
![[Up: ME_INV_A_58 h4]](v2html-up.gif)
module ME_INV_A_10
(A, Z);
input [9:0] A
;
output [9:0] Z
;
JINVA g0 (.O(Z[0]), .A(A[0]) );
JINVA g1 (.O(Z[1]), .A(A[1]) );
JINVA g2 (.O(Z[2]), .A(A[2]) );
JINVA g3 (.O(Z[3]), .A(A[3]) );
JINVA g4 (.O(Z[4]), .A(A[4]) );
JINVA g5 (.O(Z[5]), .A(A[5]) );
JINVA g6 (.O(Z[6]), .A(A[6]) );
JINVA g7 (.O(Z[7]), .A(A[7]) );
JINVA g8 (.O(Z[8]), .A(A[8]) );
JINVA g9 (.O(Z[9]), .A(A[9]) );
endmodule
module ME_INV_A_58
(A, Z);
input [57:0] A
;
output [57:0] Z
;
ME_INV_A_10 h0 (A[9:0], Z[9:0]);
ME_INV_A_10 h2 (A[19:10], Z[19:10]);
ME_INV_A_10 h3 (A[29:20], Z[29:20]);
ME_INV_A_10 h4 (A[39:30], Z[39:30]);
ME_INV_A_10 h5 (A[49:40], Z[49:40]);
ME_INV_A g0 (A[50], Z[50]);
ME_INV_A g1 (A[51], Z[51]);
ME_INV_A g2 (A[52], Z[52]);
ME_INV_A g3 (A[53], Z[53]);
ME_INV_A g4 (A[54], Z[54]);
ME_INV_A g5 (A[55], Z[55]);
ME_INV_A g6 (A[56], Z[56]);
ME_INV_A g7 (A[57], Z[57]);
endmodule
![[Up: ME_MUX_2B_11 b1]](v2html-up.gif)
![[Up: ME_MUX_2B_11 b2]](v2html-up.gif)
![[Up: ME_MUX_2B_13 g10]](v2html-up.gif)
![[Up: ME_MUX_2B_B_13 g10]](v2html-up.gif)
![[Up: stat_ctl b0]](v2html-up.gif)
![[Up: carrysaveregslsb g00]](v2html-up.gif)
![[Up: carrysaveregslsb g02]](v2html-up.gif)
![[Up: ME_MUX_2B_2 g10]](v2html-up.gif)
![[Up: ME_MUX_2B_3 g10]](v2html-up.gif)
![[Up: ME_MUX_2B_4 g10]](v2html-up.gif)
![[Up: ME_MUX_2B_5 g10]](v2html-up.gif)
![[Up: ME_MUX_2B_9 g10]](v2html-up.gif)
module ME_BUFF
(a, x);
input a
;
output x
;
JBUFC i (.O(x), .A(a) );
endmodule
![[Up: acell1a g6]](v2html-up.gif)
![[Up: acell1 g6]](v2html-up.gif)
![[Up: ME_MUX_2B_64 g10]](v2html-up.gif)
![[Up: ME_MUX_4B_10 g11]](v2html-up.gif)
![[Up: ME_MUX_4B_13 g11]](v2html-up.gif)
![[Up: MISelect mie0]](v2html-up.gif)
![[Up: ME_FREGA_1_11 m20]](v2html-up.gif)
module ME_BUF_B
(a, x); // Same as ME_BUFF
input a
;
output x
;
JBUFD i (.O(x), .A(a) );
endmodule
![[Up: ME_FREGA_S_4_13 m20]](v2html-up.gif)
![[Up: ME_FREGA_S_4_13 m21]](v2html-up.gif)
![[Up: ME_FREGA_S_4_13 m22]](v2html-up.gif)
![[Up: ME_MUX_2B_64 g11]](v2html-up.gif)
![[Up: ME_MUX_2B_64 g12]](v2html-up.gif)
![[Up: ME_MUX_4B_10 g10]](v2html-up.gif)
![[Up: ME_MUX_4B_13 g10]](v2html-up.gif)
![[Up: ME_FREGA_4_13 m20]](v2html-up.gif)
![[Up: ME_FREGA_4_13 m21]](v2html-up.gif)
![[Up: ME_FREGA_4_13 m22]](v2html-up.gif)
![[Up: ME_MUX3_25 b0]](v2html-up.gif)
![[Up: ME_MUX3_25 b1]](v2html-up.gif)
![[Up: ME_MUX3_25 b2]](v2html-up.gif)
![[Up: ME_MUX3_25 b3]](v2html-up.gif)
![[Up: ME_BUF3_4 i0]](v2html-up.gif)
![[Up: ME_BUF3_4 i1]](v2html-up.gif)
![[Up: ME_BUF3_4 i2]](v2html-up.gif)
![[Up: ME_BUF3_4 i3]](v2html-up.gif)
![[Up: ME_MUX3_53 b0]](v2html-up.gif)
![[Up: ME_MUX3_53 b1]](v2html-up.gif)
![[Up: ME_MUX3_53 b2]](v2html-up.gif)
![[Up: ME_MUX3_53 b3]](v2html-up.gif)
![[Up: ME_MUX3_53 b4]](v2html-up.gif)
![[Up: ME_MUX3_53 b5]](v2html-up.gif)
![[Up: ME_MUX3_53 b6]](v2html-up.gif)
![[Up: ME_MUX3_53 b7]](v2html-up.gif)
![[Up: ME_MUX41H28 b0]](v2html-up.gif)
![[Up: ME_MUX41H28 b1]](v2html-up.gif)
![[Up: ME_MUX41H28 b2]](v2html-up.gif)
![[Up: ME_MUX41H28 b3]](v2html-up.gif)
![[Up: ME_MUX41H32 b0]](v2html-up.gif)
... (truncated)
module ME_BUF_C
(a, x); // Same as ME_BUFF
input a
;
output x
;
JBUFD i (.O(x), .A(a) );
endmodule
![[Up: ME_MUX21H23 b10]](v2html-up.gif)
![[Up: ME_MUX21H25 b10]](v2html-up.gif)
![[Up: ME_MUX21H30 b10]](v2html-up.gif)
![[Up: ME_MUX21H32 b10]](v2html-up.gif)
module ME_BUF_D
(a, x); // Same as ME_BUFF
input a
;
output x
;
JBUFE i (.O(x), .A(a) );
endmodule
module ME_BUF3_4
( a, x );
input [3:0] a
;
output [3:0] x
;
ME_BUF_C i0 (a[0], x[0]);
ME_BUF_C i1 (a[1], x[1]);
ME_BUF_C i2 (a[2], x[2]);
ME_BUF_C i3 (a[3], x[3]);
endmodule
![[Up: fp_qst fpst_buff1]](v2html-up.gif)
module ME_BUF32_C
( a, x );
input [31:0] a
;
output [31:0] x
;
JBUFC i0 (.O(x[0]), .A(a[0]) );
JBUFC i1 (.O(x[1]), .A(a[1]) );
JBUFC i2 (.O(x[2]), .A(a[2]) );
JBUFC i3 (.O(x[3]), .A(a[3]) );
JBUFC i4 (.O(x[4]), .A(a[4]) );
JBUFC i5 (.O(x[5]), .A(a[5]) );
JBUFC i6 (.O(x[6]), .A(a[6]) );
JBUFC i7 (.O(x[7]), .A(a[7]) );
JBUFC i8 (.O(x[8]), .A(a[8]) );
JBUFC i9 (.O(x[9]), .A(a[9]) );
JBUFC i10 (.O(x[10]), .A(a[10]) );
JBUFC i11 (.O(x[11]), .A(a[11]) );
JBUFC i12 (.O(x[12]), .A(a[12]) );
JBUFC i13 (.O(x[13]), .A(a[13]) );
JBUFC i14 (.O(x[14]), .A(a[14]) );
JBUFC i15 (.O(x[15]), .A(a[15]) );
JBUFC i16 (.O(x[16]), .A(a[16]) );
JBUFC i17 (.O(x[17]), .A(a[17]) );
JBUFC i18 (.O(x[18]), .A(a[18]) );
JBUFC i19 (.O(x[19]), .A(a[19]) );
JBUFC i20 (.O(x[20]), .A(a[20]) );
JBUFC i21 (.O(x[21]), .A(a[21]) );
JBUFC i22 (.O(x[22]), .A(a[22]) );
JBUFC i23 (.O(x[23]), .A(a[23]) );
JBUFC i24 (.O(x[24]), .A(a[24]) );
JBUFC i25 (.O(x[25]), .A(a[25]) );
JBUFC i26 (.O(x[26]), .A(a[26]) );
JBUFC i27 (.O(x[27]), .A(a[27]) );
JBUFC i28 (.O(x[28]), .A(a[28]) );
JBUFC i29 (.O(x[29]), .A(a[29]) );
JBUFC i30 (.O(x[30]), .A(a[30]) );
JBUFC i31 (.O(x[31]), .A(a[31]) );
endmodule
![[Up: DecodeCmpAndNeg dcep2]](v2html-up.gif)
![[Up: DecodeCmpAndNeg dcep3]](v2html-up.gif)
![[Up: EntryCheck g_3]](v2html-up.gif)
![[Up: EntryCheck h_4]](v2html-up.gif)
![[Up: EntryCheck h_6]](v2html-up.gif)
![[Up: EntryCheck j_3]](v2html-up.gif)
![[Up: CondMux vc_3]](v2html-up.gif)
![[Up: acell10 g10]](v2html-up.gif)
![[Up: acell16 g10]](v2html-up.gif)
![[Up: acell16 g11]](v2html-up.gif)
![[Up: SignDp rg4]](v2html-up.gif)
![[Up: SignDp rzz1s]](v2html-up.gif)
![[Up: SignDp rv2]](v2html-up.gif)
![[Up: SignDp rv3]](v2html-up.gif)
![[Up: StickyPairNC g22]](v2html-up.gif)
![[Up: StickyPairNC g14]](v2html-up.gif)
![[Up: StickyPairNC g32]](v2html-up.gif)
![[Up: acell4a g10]](v2html-up.gif)
![[Up: acell4a g11]](v2html-up.gif)
![[Up: MIptr om16]](v2html-up.gif)
![[Up: acell4 g10]](v2html-up.gif)
![[Up: acell4 g11]](v2html-up.gif)
![[Up: SignLogic sae1]](v2html-up.gif)
![[Up: ExpShifter g15]](v2html-up.gif)
![[Up: ExpShifter g32]](v2html-up.gif)
![[Up: NullExcepLogic re]](v2html-up.gif)
![[Up: NullExcepLogic g_1]](v2html-up.gif)
![[Up: NullExcepLogic exg1]](v2html-up.gif)
![[Up: NullExcepLogic exg2]](v2html-up.gif)
![[Up: NullExcepLogic eag2]](v2html-up.gif)
![[Up: NullExcepLogic eag5]](v2html-up.gif)
... (truncated)
module ME_NAND2
(a, b, z);
input a
, b
;
output z
;
JNAND2A i (.O(z), .A1(a), .A2(b) );
endmodule
![[Up: ExpConstantCtl z07]](v2html-up.gif)
![[Up: SignDp rv03]](v2html-up.gif)
![[Up: SignDp rvo2]](v2html-up.gif)
![[Up: SignDp rvo1]](v2html-up.gif)
![[Up: notonesch i2]](v2html-up.gif)
![[Up: NullExcepLogic yyd]](v2html-up.gif)
![[Up: StickyPairNCI g32]](v2html-up.gif)
![[Up: adder13 g14]](v2html-up.gif)
![[Up: adder13 g16]](v2html-up.gif)
![[Up: adder58 g14]](v2html-up.gif)
![[Up: adder58 g16]](v2html-up.gif)
![[Up: onesch_sp i2]](v2html-up.gif)
![[Up: onesch_sp i3]](v2html-up.gif)
![[Up: onesch_sp r5]](v2html-up.gif)
![[Up: MulSelCtl nzr8]](v2html-up.gif)
![[Up: ImplementedCheck g_3]](v2html-up.gif)
module ME_NAND2_B
(a, b, z);
input a
, b
;
output z
;
JNAND2B i (.O(z), .A1(a), .A2(b) );
endmodule
![[Up: EntryCheck g_6]](v2html-up.gif)
![[Up: EntryCheck g_9]](v2html-up.gif)
![[Up: EntryCheck h_2]](v2html-up.gif)
![[Up: EntryCheck h_8]](v2html-up.gif)
![[Up: EntryCheck h_9]](v2html-up.gif)
![[Up: acell10 g20]](v2html-up.gif)
![[Up: acell16 g21]](v2html-up.gif)
![[Up: StickyPairNC g20]](v2html-up.gif)
![[Up: StickyPairNC g21]](v2html-up.gif)
![[Up: StickyPairNC g23]](v2html-up.gif)
![[Up: StickyPairNC g24]](v2html-up.gif)
![[Up: acell4a g21]](v2html-up.gif)
![[Up: acell4 g21]](v2html-up.gif)
![[Up: SignLogic sbe]](v2html-up.gif)
![[Up: ExpShifter g12]](v2html-up.gif)
![[Up: ShiftDec g20]](v2html-up.gif)
![[Up: DecodeStatus p1]](v2html-up.gif)
![[Up: DecodeStatus p2]](v2html-up.gif)
![[Up: DecodeStatus p3]](v2html-up.gif)
![[Up: StickyPairNCI g20]](v2html-up.gif)
![[Up: StickyPairNCI g21]](v2html-up.gif)
![[Up: StickyPairNCI g23]](v2html-up.gif)
![[Up: ShiftRightCtl g13]](v2html-up.gif)
![[Up: AregInexact aig13]](v2html-up.gif)
![[Up: MISelect g4_0]](v2html-up.gif)
![[Up: MulSelCtl nzr6]](v2html-up.gif)
![[Up: DivLog qb1t0]](v2html-up.gif)
![[Up: DivLog qb1t3]](v2html-up.gif)
![[Up: DivLog qb1t4]](v2html-up.gif)
![[Up: ImplementedCheck ggh4]](v2html-up.gif)
![[Up: ImplementedCheck ddfd]](v2html-up.gif)
... (truncated)
module ME_NAND3
(a, b, c, z);
input a
, b
, c
;
output z
;
JNAND3A i (.O(z), .A1(a), .A2(b), .A3(c) );
endmodule
![[Up: ExpConstantCtl z06]](v2html-up.gif)
![[Up: StickyPairNCI g25]](v2html-up.gif)
![[Up: PreventSwapCtl psg4]](v2html-up.gif)
![[Up: CaseGeneration nrc]](v2html-up.gif)
![[Up: MISelect g0_0]](v2html-up.gif)
![[Up: ResultException g23]](v2html-up.gif)
module ME_NAND3_B
(a, b, c, z);
input a
, b
, c
;
output z
;
JNAND3B i (.O(z), .A1(a), .A2(b), .A3(c) );
endmodule
![[Up: EntryCheck g_4]](v2html-up.gif)
![[Up: EntryCheck j_1]](v2html-up.gif)
![[Up: twosch_top m5]](v2html-up.gif)
![[Up: AregInexactSlice ai27]](v2html-up.gif)
![[Up: AregInexactSlice ai17]](v2html-up.gif)
![[Up: DecodeStatus p0]](v2html-up.gif)
![[Up: ShiftRightCtl g81]](v2html-up.gif)
![[Up: YMuxCtl ymlsbs4]](v2html-up.gif)
![[Up: YMuxCtl ymlsbs8]](v2html-up.gif)
![[Up: PreventSwapCtl psg5]](v2html-up.gif)
![[Up: DivLog ds10]](v2html-up.gif)
![[Up: DivLog ds11]](v2html-up.gif)
![[Up: DivLog ds20]](v2html-up.gif)
![[Up: DivLog ds21]](v2html-up.gif)
![[Up: DivLog ds22]](v2html-up.gif)
![[Up: DivLog ds23]](v2html-up.gif)
![[Up: DivLog ds2m]](v2html-up.gif)
![[Up: DivLog ds31]](v2html-up.gif)
![[Up: DivLog ds33]](v2html-up.gif)
module ME_NAND4
(a, b, c, d, z);
input a
, b
, c
, d
;
output z
;
JNAND4A i (.O(z), .A1(a), .A2(b), .A3(c), .A4(d) );
endmodule
module ME_NAND5
(a, b, c, d, e, z);
input a
, b
, c
, d
, e
;
output z
;
ANAND5C i (.O(z), .A1(a), .A2(b), .A3(c), .A4(d), .A5(e) );
endmodule
module ME_NAND6_B
(a, b, c, d, e, f, z);
input a
, b
, c
, d
, e
, f
;
output z
;
JNAND6C i (.O(z), .A1(a), .A2(b), .A3(c), .A4(d), .A5(e), .A6(f) );
endmodule
module ME_NAND8
(a, b, c, d, e, f, g, h, z);
input a
, b
, c
, d
, e
, f
, g
, h
;
output z
;
JNAND8C i (.O(z), .A1(a), .A2(b), .A3(c), .A4(d), .A5(e), .A6(f),
.A7(g), .A8(h) );
endmodule
module ME_NAND8_B
(a, b, c, d, e, f, g, h, z);
input a
, b
, c
, d
, e
, f
, g
, h
;
output z
;
JNAND8C i (.O(z), .A1(a), .A2(b), .A3(c), .A4(d), .A5(e), .A6(f),
.A7(g), .A8(h) );
endmodule
// AND gates
![[Up: TregLoadCtl ftlt]](v2html-up.gif)
![[Up: EntryCheck g_8]](v2html-up.gif)
![[Up: EntryCheck h_1]](v2html-up.gif)
![[Up: CondMux c_2]](v2html-up.gif)
![[Up: CondMux c_3]](v2html-up.gif)
![[Up: CondMux c_4]](v2html-up.gif)
![[Up: CondMux sp_1]](v2html-up.gif)
![[Up: SignDp v2]](v2html-up.gif)
![[Up: BregLoadCtl ssg81]](v2html-up.gif)
![[Up: BregLoadCtl ssg80]](v2html-up.gif)
![[Up: BregLoadCtl alcn3]](v2html-up.gif)
![[Up: BregLoadCtl alcn2]](v2html-up.gif)
![[Up: BregLoadCtl alcn1]](v2html-up.gif)
![[Up: BregLoadCtl alcni]](v2html-up.gif)
![[Up: RoundModeLogic rmcmp1]](v2html-up.gif)
![[Up: RoundModeLogic rmc]](v2html-up.gif)
![[Up: ExpShifter gr5]](v2html-up.gif)
![[Up: NullExcepLogic rb]](v2html-up.gif)
![[Up: NullExcepLogic eag1]](v2html-up.gif)
![[Up: DecodeStatus b1]](v2html-up.gif)
![[Up: adder13 g20]](v2html-up.gif)
![[Up: adder13 g21]](v2html-up.gif)
![[Up: ShiftRightCtl g12]](v2html-up.gif)
![[Up: AregLoadCtl alcn1]](v2html-up.gif)
![[Up: AregLoadCtl alcn2]](v2html-up.gif)
![[Up: AregLoadCtl alcn3]](v2html-up.gif)
![[Up: AregLoadCtl alcni]](v2html-up.gif)
![[Up: ExpRegLoadCtl alcn1]](v2html-up.gif)
![[Up: ExpRegLoadCtl alcn2]](v2html-up.gif)
![[Up: CaseGeneration ril]](v2html-up.gif)
![[Up: adder58 g20]](v2html-up.gif)
... (truncated)
module ME_AND2
(a, b, z);
input a
, b
;
output z
;
JAND2B i (.O(z), .A1(a), .A2(b) );
endmodule
![[Up: ExpConstantCtl z01]](v2html-up.gif)
![[Up: ExpConstantCtl z02]](v2html-up.gif)
![[Up: CondMux c_0]](v2html-up.gif)
![[Up: CondMux c_1]](v2html-up.gif)
![[Up: SignDp s1]](v2html-up.gif)
![[Up: SignDp s3]](v2html-up.gif)
![[Up: SignDp s4]](v2html-up.gif)
![[Up: notonesch i3]](v2html-up.gif)
![[Up: notonesch r4]](v2html-up.gif)
![[Up: notonesch r5]](v2html-up.gif)
![[Up: CS_byte g02]](v2html-up.gif)
![[Up: CS_byte g12]](v2html-up.gif)
![[Up: CS_byte g22]](v2html-up.gif)
![[Up: CS_byte g32]](v2html-up.gif)
![[Up: CS_byte g42]](v2html-up.gif)
![[Up: CS_byte g52]](v2html-up.gif)
![[Up: CS_byte g62]](v2html-up.gif)
![[Up: CS_byte g72]](v2html-up.gif)
![[Up: CS_bit g12]](v2html-up.gif)
![[Up: RoundModeLogic fgf]](v2html-up.gif)
![[Up: ExpShifter a90]](v2html-up.gif)
![[Up: NullExcepLogic cko]](v2html-up.gif)
module ME_AND2_B
(a, b, z);
input a
, b
;
output z
;
JAND2B i (.O(z), .A1(a), .A2(b) );
endmodule
![[Up: DecodeStatus b0]](v2html-up.gif)
![[Up: DecodeStatus b3]](v2html-up.gif)
![[Up: DecodeStatus b4]](v2html-up.gif)
![[Up: ShiftRightCtl g88]](v2html-up.gif)
![[Up: AregLoadCtl alcnf]](v2html-up.gif)
![[Up: CaseGeneration cqsb]](v2html-up.gif)
![[Up: SampledWaitCtl g1_0]](v2html-up.gif)
![[Up: CregLoadCtl fg1d]](v2html-up.gif)
module ME_AND3
(a, b, c, z);
input a
, b
, c
;
output z
;
JAND3B i (.O(z), .A1(a), .A2(b), .A3(c) );
endmodule
![[Up: ExpConstantCtl z00]](v2html-up.gif)
![[Up: CondMux h_0]](v2html-up.gif)
![[Up: SignDp s2]](v2html-up.gif)
![[Up: YMuxCtl fs3]](v2html-up.gif)
![[Up: AregLoadCtl alcnh]](v2html-up.gif)
![[Up: Exception g20]](v2html-up.gif)
module ME_AND3_B
(a, b, c, z);
input a
, b
, c
;
output z
;
JAND3B i (.O(z), .A1(a), .A2(b), .A3(c) );
endmodule
![[Up: DecodeCmpAndNeg dcep7]](v2html-up.gif)
![[Up: EntryCheck j_2]](v2html-up.gif)
![[Up: CondMux sp_0]](v2html-up.gif)
![[Up: NullExcepLogic ssss]](v2html-up.gif)
![[Up: DecodeStatus b2]](v2html-up.gif)
![[Up: MISelect g4_6]](v2html-up.gif)
![[Up: MISelect ggh7]](v2html-up.gif)
module ME_AND4
(a, b, c, d, z);
input a
, b
, c
, d
;
output z
;
JAND4B i (.O(z), .A1(a), .A2(b), .A3(c), .A4(d) );
endmodule
![[Up: acell10 g27]](v2html-up.gif)
![[Up: acell16 g27]](v2html-up.gif)
![[Up: acell4a g26]](v2html-up.gif)
![[Up: acell4 g26]](v2html-up.gif)
![[Up: ResultException zze]](v2html-up.gif)
module ME_AND4_B
(a, b, c, d, z);
input a
, b
, c
, d
;
output z
;
JAND4B i (.O(z), .A1(a), .A2(b), .A3(c), .A4(d) );
endmodule
module ME_AND7
( a1, a2, a3, a4, a5, a6, a7, z );
input a1
, a2
, a3
, a4
, a5
, a6
, a7
;
output z
;
wire x1
, x2
;
JNAND3A i0 (.O(x1), .A1(a1), .A2(a2), .A3(a3) );
JNAND4A i1 (.O(x2), .A1(a4), .A2(a5), .A3(a6), .A4(a7) );
JNOR2A i2 (.O(z), .A1(x1), .A2(x2) );
endmodule
module ME_AND8
(a, b, c, d, e, f, g, h, z);
input a
, b
, c
, d
, e
, f
, g
, h
;
output z
;
JAND8B i (.O(z), .A1(a), .A2(b), .A3(c), .A4(d), .A5(e), .A6(f),
.A7(g), .A8(h) );
endmodule
// nor gates
![[Up: DecodeCmpAndNeg decep8]](v2html-up.gif)
![[Up: EntryCheck g_2]](v2html-up.gif)
![[Up: EntryCheck h_7]](v2html-up.gif)
![[Up: SignDp v3]](v2html-up.gif)
![[Up: AregInexactSlice aig5]](v2html-up.gif)
![[Up: AregInexactSlice aizz]](v2html-up.gif)
![[Up: SignLogic stg7]](v2html-up.gif)
![[Up: SignLogic stg8]](v2html-up.gif)
![[Up: SignLogic stg9]](v2html-up.gif)
![[Up: SignLogic stgA]](v2html-up.gif)
![[Up: SignLogic stgB]](v2html-up.gif)
![[Up: qcore_ctl iu_hold_gate_14]](v2html-up.gif)
![[Up: ExpShifter sby8]](v2html-up.gif)
![[Up: onesch i2]](v2html-up.gif)
![[Up: SampledWaitCtl swmzs]](v2html-up.gif)
![[Up: CregLoadCtl icr]](v2html-up.gif)
![[Up: CregLoadCtl rct]](v2html-up.gif)
module ME_NOR2
(a, b, z);
input a
, b
;
output z
;
JNOR2A i (.O(z), .A1(a), .A2(b) );
endmodule
![[Up: qcore_ctl iu_hold_gate_1]](v2html-up.gif)
![[Up: qcore_ctl iu_hold_gate_2]](v2html-up.gif)
![[Up: qcore_ctl iu_hold_gate_3]](v2html-up.gif)
![[Up: onesch r4]](v2html-up.gif)
module ME_NOR2_B
(a, b, z);
input a
, b
;
output z
;
JNOR2C i (.O(z), .A1(a), .A2(b) );
endmodule
module ME_NOR2_D
(a, b, z);
input a
, b
;
output z
;
JNOR2D i (.O(z), .A1(a), .A2(b) );
endmodule
![[Up: EntryCheck g_1]](v2html-up.gif)
![[Up: EntryCheck g_0]](v2html-up.gif)
![[Up: EntryCheck h_3]](v2html-up.gif)
![[Up: EntryCheck h_5]](v2html-up.gif)
![[Up: AregInexactSlice aig0]](v2html-up.gif)
![[Up: AregInexactSlice aig6]](v2html-up.gif)
![[Up: RoundModeLogic rmcmpe1]](v2html-up.gif)
![[Up: RoundModeLogic rmcmpe0]](v2html-up.gif)
![[Up: qcore_ctl iu_hold_gate_33]](v2html-up.gif)
module ME_NOR3
(a, b, c, z);
input a
, b
, c
;
output z
;
JNOR3C i (.O(z), .A1(a), .A2(b), .A3(c) );
endmodule
![[Up: EntryCheck g_7]](v2html-up.gif)
![[Up: AregInexactSlice ai54]](v2html-up.gif)
![[Up: AregInexactSlice ai44]](v2html-up.gif)
![[Up: AregInexactSlice ai34]](v2html-up.gif)
![[Up: AregInexactSlice ai24]](v2html-up.gif)
![[Up: AregInexactSlice ai14]](v2html-up.gif)
![[Up: AregInexactSlice ai04]](v2html-up.gif)
module ME_NOR4
(a, b, c, d, z);
input a
, b
, c
, d
;
output z
;
JNOR4B i (.O(z), .A1(a), .A2(b), .A3(c), .A4(d) );
endmodule
module ME_NOR6_B
(a, b, c, d, e, f, z);
input a
, b
, c
, d
, e
, f
;
output z
;
JNOR6C i (.O(z), .A1(a), .A2(b), .A3(c), .A4(d), .A5(e), .A6(f) );
endmodule
![[Up: SignDp rc0]](v2html-up.gif)
![[Up: MicrocodeRom Uscanloadrom]](v2html-up.gif)
![[Up: MIptr om2n6]](v2html-up.gif)
![[Up: SignLogic orr]](v2html-up.gif)
![[Up: SignLogic gbdf]](v2html-up.gif)
![[Up: SignLogic codie]](v2html-up.gif)
![[Up: NullExcepLogic eag3]](v2html-up.gif)
![[Up: NullExcepLogic yyy]](v2html-up.gif)
![[Up: ShiftRightCtl g85]](v2html-up.gif)
![[Up: SampleReset cva]](v2html-up.gif)
![[Up: onesch i3]](v2html-up.gif)
![[Up: ImplementedCheck idg1]](v2html-up.gif)
![[Up: ImplementedCheck idg4]](v2html-up.gif)
![[Up: ImplementedCheck ggh3]](v2html-up.gif)
![[Up: ImplementedCheck icor]](v2html-up.gif)
![[Up: SampledWaitCtl swmis]](v2html-up.gif)
module ME_OR2
(a, b, z);
input a
, b
;
output z
;
JOR2B i (.O(z), .A1(a), .A2(b) );
endmodule
![[Up: ExpConstantCtl z03]](v2html-up.gif)
![[Up: ExpConstantCtl z04]](v2html-up.gif)
![[Up: fp_qst iu_hold_gate_1]](v2html-up.gif)
![[Up: fp_qst iu_hold_gate_2]](v2html-up.gif)
![[Up: fp_qst iu_hold_gate_3]](v2html-up.gif)
![[Up: fp_qst iu_hold_gate_4]](v2html-up.gif)
![[Up: StickyPairNC g13]](v2html-up.gif)
![[Up: RoundModeLogic fgfo]](v2html-up.gif)
![[Up: NullExcepLogic exg3]](v2html-up.gif)
![[Up: NullExcepLogic yyb]](v2html-up.gif)
![[Up: StickyPairNCI g13]](v2html-up.gif)
![[Up: stat_ctl iu_hold_gate_8]](v2html-up.gif)
![[Up: ShiftRight h01]](v2html-up.gif)
![[Up: ShiftRight h02]](v2html-up.gif)
![[Up: ShiftRight h03]](v2html-up.gif)
![[Up: ShiftRight h04]](v2html-up.gif)
![[Up: ShiftRight h05]](v2html-up.gif)
![[Up: ShiftRight h06]](v2html-up.gif)
![[Up: ShiftRight h07]](v2html-up.gif)
![[Up: ShiftRight h08]](v2html-up.gif)
![[Up: ShiftRight h09]](v2html-up.gif)
![[Up: ShiftRight h10]](v2html-up.gif)
![[Up: ShiftRight h11]](v2html-up.gif)
![[Up: ShiftRight h12]](v2html-up.gif)
![[Up: ShiftRight h13]](v2html-up.gif)
![[Up: ShiftRight h14]](v2html-up.gif)
![[Up: ShiftRight h15]](v2html-up.gif)
![[Up: ShiftRight h16]](v2html-up.gif)
![[Up: ShiftRight h17]](v2html-up.gif)
![[Up: ShiftRight h18]](v2html-up.gif)
![[Up: ShiftRight h19]](v2html-up.gif)
... (truncated)
module ME_OR2_B
(a, b, z);
input a
, b
;
output z
;
JOR2B i (.O(z), .A1(a), .A2(b) );
endmodule
![[Up: ExpRegLoadCtl alcne]](v2html-up.gif)
![[Up: Exception zxe]](v2html-up.gif)
module ME_OR3
(a, b, c, z);
input a
, b
, c
;
output z
;
JOR3B i (.O(z), .A1(a), .A2(b), .A3(c) );
endmodule
![[Up: MulSelCtl nzr5]](v2html-up.gif)
![[Up: CheckOverflow srgx]](v2html-up.gif)
module ME_OR3_B
(a, b, c, z);
input a
, b
, c
;
output z
;
JOR3B i (.O(z), .A1(a), .A2(b), .A3(c) );
endmodule
![[Up: BregLoadCtl alcne]](v2html-up.gif)
![[Up: SignLogic ggdf]](v2html-up.gif)
module ME_OR4
(a, b, c, d, z);
input a
, b
, c
, d
;
output z
;
JOR4B i (.O(z), .A1(a), .A2(b), .A3(c), .A4(d) );
endmodule
module ME_OR6
(a, b, c, d, e, f, X);
input a
, b
, c
, d
, e
, f
;
output X
;
JOR6B i (.O(X), .A1(a), .A2(b), .A3(c), .A4(d), .A5(e), .A6(f) );
endmodule
module ME_OR8
(a, b, c, d, e, f, g, h, X);
input a
, b
, c
, d
, e
, f
, g
, h
;
output X
;
JOR8B i (.O(X), .A1(a), .A2(b), .A3(c), .A4(d), .A5(e), .A6(f),
.A7(g), .A8(h) );
endmodule
module ME_OR11
(a, b, c, d, e, f, g, h, i, j, k, X);
input a
, b
, c
, d
, e
, f
, g
, h
, i
, j
, k
;
output X
;
wire x0
, x1
;
JNOR8C u0 (.O(x0), .A1(a), .A2(b), .A3(c), .A4(d), .A5(e), .A6(f),
.A7(g), .A8(h) );
JNOR3A u1 (.O(x1), .A1(i), .A2(j), .A3(k) );
JNAND2A u2 (.O(X), .A1(x0), .A2(x1) );
endmodule
module ME_OR12
(a, b, c, d, e, f, g, h, i, j, k, l, X);
input a
, b
, c
, d
, e
, f
, g
, h
, i
, j
, k
, l
;
output X
;
wire x0
, x1
;
JNOR8C u0 (.O(x0), .A1(a), .A2(b), .A3(c), .A4(d), .A5(e), .A6(f),
.A7(g), .A8(h) );
JNOR4B u1 (.O(x1), .A1(i), .A2(j), .A3(k), .A4(l) );
JNAND2A u2 (.O(X), .A1(x0), .A2(x1) );
endmodule
module ME_XNOR2
(a, b, z);
input a
, b
;
output z
;
JXNOR2A i (.O(z), .A1(a), .A2(b) );
endmodule
![[Up: StickyPairNC g10]](v2html-up.gif)
![[Up: StickyPairNC g11]](v2html-up.gif)
![[Up: CS_byte g00]](v2html-up.gif)
![[Up: CS_byte g10]](v2html-up.gif)
![[Up: CS_byte g20]](v2html-up.gif)
![[Up: CS_byte g30]](v2html-up.gif)
![[Up: CS_byte g40]](v2html-up.gif)
![[Up: CS_byte g50]](v2html-up.gif)
![[Up: CS_byte g60]](v2html-up.gif)
![[Up: CS_byte g70]](v2html-up.gif)
![[Up: CS_bit g10]](v2html-up.gif)
![[Up: SignLogic u0_v1]](v2html-up.gif)
![[Up: SignLogic u0_v2]](v2html-up.gif)
![[Up: StickyPairNCI g10]](v2html-up.gif)
module ME_XNOR2_B
(a, b, z);
input a
, b
;
output z
;
JXNOR2B i (.O(z), .A1(a), .A2(b) );
endmodule
![[Up: EntryCheck g_5]](v2html-up.gif)
![[Up: SignLogic xorabs]](v2html-up.gif)
![[Up: SignLogic xorop]](v2html-up.gif)
![[Up: MiptrIncrement ha_7]](v2html-up.gif)
module ME_XOR2
(a, b, z);
input a
, b
;
output z
;
JXOR2A i (.O(z), .A1(a), .A2(b) );
endmodule
![[Up: CondMux vd_0]](v2html-up.gif)
module ME_XOR2_B
(a, b, z);
input a
, b
;
output z
;
JXOR2B i (.O(z), .A1(a), .A2(b) );
endmodule
![[Up: acell1a g1]](v2html-up.gif)
![[Up: StickyPairNC g26]](v2html-up.gif)
![[Up: acell1 g1]](v2html-up.gif)
module ME_XOR3_B
(a, b, c, z);
input a
, b
, c
;
output z
;
JXOR3A i (.O(z), .A1(a), .A2(b), .A3(c) );
endmodule
// Matrix gates
![[Up: rfrw_ctl iu_hold_gate_4]](v2html-up.gif)
![[Up: rfrw_ctl iu_hold_gate_5]](v2html-up.gif)
![[Up: qcore_ctl iu_hold_gate_9]](v2html-up.gif)
![[Up: qcore_ctl iu_hold_gate_10]](v2html-up.gif)
![[Up: qcore_ctl iu_hold_gate_11]](v2html-up.gif)
![[Up: qcore_ctl iu_hold_gate_22]](v2html-up.gif)
module ME_A2O1_B
(a, b, c, z); // z = (a&b) | c
input a
, b
, c
;
output z
;
JDB21A i (.O(z), .A1(a), .A2(b), .B(c) );
endmodule
![[Up: rfrw_ctl iu_hold_gate_6]](v2html-up.gif)
![[Up: rfrw_ctl iu_hold_gate_7]](v2html-up.gif)
![[Up: rfrw_ctl iu_hold_gate_8]](v2html-up.gif)
![[Up: rfrw_ctl iu_hold_gate_9]](v2html-up.gif)
![[Up: rfrw_ctl iu_hold_gate_10]](v2html-up.gif)
![[Up: rfrw_ctl iu_hold_gate_11]](v2html-up.gif)
![[Up: qcore_ctl iu_hold_gate_7]](v2html-up.gif)
![[Up: qcore_ctl iu_hold_gate_8]](v2html-up.gif)
![[Up: qcore_ctl iu_hold_gate_15]](v2html-up.gif)
![[Up: qcore_ctl iu_hold_gate_16]](v2html-up.gif)
![[Up: qcore_ctl iu_hold_gate_17]](v2html-up.gif)
![[Up: qcore_ctl iu_hold_gate_12]](v2html-up.gif)
![[Up: qcore_ctl iu_hold_gate_13]](v2html-up.gif)
![[Up: fhold_ctl iu_hold_gate_3]](v2html-up.gif)
module ME_AI2O1_C
(a, b, c, z); // z = (a & ~b) | c
input a
, b
, c
;
output z
;
ADBI21C i (.O(z), .A1(a), .A2(b), .B(c) );
endmodule
module ME_AI2O1_D
(a, b, c, z); // z = (a & ~b) | c
input a
, b
, c
;
output z
;
ADBI21D i (.O(z), .A1(a), .A2(b), .B(c) );
endmodule
module ME_A22O1_B
(a1, a2, b1, b2, c, z); // z = (a1&a2) | (b1&b2) | c;
input a1
, a2
, b1
, b2
, c
;
output z
;
JDB122A i (.O(z), .A1(a1), .A2(a2), .B1(b1), .B2(b2), .C(c) );
endmodule
![[Up: qcore_ctl iu_hold_gate_25]](v2html-up.gif)
![[Up: qcore_ctl iu_hold_gate_26]](v2html-up.gif)
![[Up: qcore_ctl iu_hold_gate_29]](v2html-up.gif)
![[Up: qcore_ctl iu_hold_gate_30]](v2html-up.gif)
![[Up: qcore_ctl iu_hold_gate_31]](v2html-up.gif)
![[Up: qcore_ctl iu_hold_gate_32]](v2html-up.gif)
![[Up: qcore_ctl iu_hold_gate_34]](v2html-up.gif)
![[Up: qcore_ctl iu_hold_gate_35]](v2html-up.gif)
![[Up: stat_ctl iu_hold_gate_3]](v2html-up.gif)
![[Up: stat_ctl iu_hold_gate_4]](v2html-up.gif)
module ME_AI22O1_C
(a1, a2, b1, b2, c, z); // z= (a1 & ~a2) | (b1&b2) | c;
input a1
, a2
, b1
, b2
, c
;
output z
;
ADBI122C i (.O(z), .A1(a1), .A2(a2), .B1(b1), .B2(b2), .C(c) );
endmodule
module ME_AI22O1_D
(a1, a2, b1, b2, c, z); // z= (a1 & ~a2) | (b1&b2) | c;
input a1
, a2
, b1
, b2
, c
;
output z
;
ADBI122D i (.O(z), .A1(a1), .A2(a2), .B1(b1), .B2(b2), .C(c) );
endmodule
module ME_AI22O1_C_2
(a1, a2, b1, b2, c, z);
input [1:0] a1
, a2
, b1
, b2
, c
;
output [1:0] z
;
ADBI122C u0 (.O(z[0]), .A1(a1[0]), .A2(a2[0]), .B1(b1[0]), .B2(b2[0]),
.C(c[0]) );
ADBI122C u1 (.O(z[1]), .A1(a1[1]), .A2(a2[1]), .B1(b1[1]), .B2(b2[1]),
.C(c[1]) );
endmodule
![[Up: stat_ctl iu_hold_gate_12]](v2html-up.gif)
module ME_AI22O1_C_5
(a1, a2, b1, b2, c, z);
input [4:0] a1
, a2
, b1
, b2
, c
;
output [4:0] z
;
ADBI122C u0 (.O(z[0]), .A1(a1[0]), .A2(a2[0]), .B1(b1[0]), .B2(b2[0]),
.C(c[0]) );
ADBI122C u1 (.O(z[1]), .A1(a1[1]), .A2(a2[1]), .B1(b1[1]), .B2(b2[1]),
.C(c[1]) );
ADBI122C u2 (.O(z[2]), .A1(a1[2]), .A2(a2[2]), .B1(b1[2]), .B2(b2[2]),
.C(c[2]) );
ADBI122C u3 (.O(z[3]), .A1(a1[3]), .A2(a2[3]), .B1(b1[3]), .B2(b2[3]),
.C(c[3]) );
ADBI122C u4 (.O(z[4]), .A1(a1[4]), .A2(a2[4]), .B1(b1[4]), .B2(b2[4]),
.C(c[4]) );
endmodule
module ME_A2O2I
(a, b, c, d, z);
input a
, b
, c
, d
;
output z
;
JD211A u1 (.O(z), .A1(a), .A2(b), .B1(c), .B2(d) );
endmodule
module ME_A2O2I_B
(a, b, c, d, z);
input a
, b
, c
, d
;
output z
;
JD211A u1 (.O(z), .A1(a), .A2(b), .B1(c), .B2(d) );
endmodule
module ME_A22OI
(a, b, c, d, z);
input a
, b
, c
, d
;
output z
;
JD22A i (.O(z), .A1(a), .A2(b), .B1(c), .B2(d) );
endmodule
module ME_A22OI_B
(a, b, c, d, z);
input a
, b
, c
, d
;
output z
;
JD22A i (.O(z), .A1(a), .A2(b), .B1(c), .B2(d) );
endmodule
module ME_O2A2I
(a, b, c, d, z);
input a
, b
, c
, d
;
output z
;
JG112A i (.O(z), .A1(a), .A2(b), .B1(c), .B2(d) );
endmodule
module ME_O2A2I_B
(a, b, c, d, z);
input a
, b
, c
, d
;
output z
;
JG112A i (.O(z), .A1(a), .A2(b), .B1(c), .B2(d) );
endmodule
module ME_O22AI
(a, b, c, d, z);
input a
, b
, c
, d
;
output z
;
JG22A i (.O(z), .A1(a), .A2(b), .B1(c), .B2(d) );
endmodule
module ME_O22AI_B
(a, b, c, d, z);
input a
, b
, c
, d
;
output z
;
JG22A i (.O(z), .A1(a), .A2(b), .B1(c), .B2(d) );
endmodule
module ME_A2O1I
(a, b, c, z);
input a
, b
, c
;
output z
;
JD21A i (.O(z), .A1(a), .A2(b), .B(c) );
endmodule
module ME_A2O1I_B
(a, b, c, z);
input a
, b
, c
;
output z
;
JD21A i (.O(z), .A1(a), .A2(b), .B(c) );
endmodule
![[Up: qcore_ctl iu_hold_gate_24]](v2html-up.gif)
![[Up: qcore_ctl iu_hold_gate_4]](v2html-up.gif)
![[Up: qcore_ctl iu_hold_gate_5]](v2html-up.gif)
![[Up: qcore_ctl iu_hold_gate_6]](v2html-up.gif)
![[Up: qcore_ctl iu_hold_gate_28]](v2html-up.gif)
![[Up: qcore_ctl iu_hold_gate_21]](v2html-up.gif)
![[Up: qcore_ctl iu_hold_gate_18]](v2html-up.gif)
![[Up: qcore_ctl iu_hold_gate_19]](v2html-up.gif)
![[Up: qcore_ctl iu_hold_gate_20]](v2html-up.gif)
![[Up: ME_FREGA_2_55 iu_hold_gate_1]](v2html-up.gif)
![[Up: stat_ctl iu_hold_gate_1]](v2html-up.gif)
![[Up: stat_ctl iu_hold_gate_2]](v2html-up.gif)
![[Up: stat_ctl iu_hold_gate_7]](v2html-up.gif)
![[Up: stat_ctl iu_hold_gate_9]](v2html-up.gif)
![[Up: stat_ctl iu_hold_gate_10]](v2html-up.gif)
module ME_O2A1
(a, b, c, z);
input a
, b
, c
;
output z
; // z = (a|b)&c
JGB12A i (.O(z), .A1(a), .A2(b), .B(c) );
endmodule
![[Up: fhold_ctl iu_hold_gate_1]](v2html-up.gif)
module ME_O2A1_D
(a, b, c, z);
input a
, b
, c
;
output z
; // z = (a|b)&c
AGB12D i (.O(z), .A1(a), .A2(b), .B(c) );
endmodule
module ME_O22A1
(a1, a2, b1, b2, c, z);
input a1
, a2
, b1
, b2
, c
;
output z
; // z = (a1 | a2) & (b1 | b2) & c
JGB221A i (.O(z), .A1(a1), .A2(a2), .B1(b1), .B2(b2), .C(c) );
endmodule
module ME_O2A1I
(a, b, c, z);
input a
, b
, c
;
output z
;
JG12A i (.O(z), .A1(a), .A2(b), .B(c) );
endmodule
module ME_O2A1I_B
(a, b, c, z);
input a
, b
, c
;
output z
;
JG12A i (.O(z), .A1(a), .A2(b), .B(c) );
endmodule
module ME_A222OI
(a, b, c, d, e, f, z);
input a
, b
, c
, d
, e
, f
;
output z
;
JD222A i (.O(z), .A1(a), .A2(b), .B1(c), .B2(d), .C1(e), .C2(f) );
endmodule
![[Up: YMuxCtl ym4]](v2html-up.gif)
![[Up: YMuxCtl ym5]](v2html-up.gif)
module ME_A222OI_B
(a, b, c, d, e, f, z);
input a
, b
, c
, d
, e
, f
;
output z
;
JD222A i (.O(z), .A1(a), .A2(b), .B1(c), .B2(d), .C1(e), .C2(f) );
endmodule
module ME_O2222AI
(a, b, c, d, e, f, g, h, z);
input a
, b
, c
, d
, e
, f
, g
, h
;
output z
;
AG2222A i (.O(z), .A1(a), .A2(b), .B1(c), .B2(d), .C1(e), .C2(f),
.D1(g), .D2(h) );
endmodule
module ME_O2222AI_B
(a, b, c, d, e, f, g, h, z);
input a
, b
, c
, d
, e
, f
, g
, h
;
output z
;
AG2222A i (.O(z), .A1(a), .A2(b), .B1(c), .B2(d), .C1(e), .C2(f),
.D1(g), .D2(h) );
endmodule
![[Up: MiptrIncrement ha_6]](v2html-up.gif)
![[Up: MiptrIncrement ha_5]](v2html-up.gif)
![[Up: MiptrIncrement ha_4]](v2html-up.gif)
![[Up: MiptrIncrement ha_3]](v2html-up.gif)
![[Up: MiptrIncrement ha_2]](v2html-up.gif)
module ME_ADD2
(a, b, s, c);
input a
, b
;
output s
,c
;
JHAD1A u0 (.CO(c), .S(s), .A(a), .B(b) );
endmodule
module ME_ADD3
(a, b, ci, s, co);
input a
, b
, ci
;
output s
, co
;
JFAD1A u0 (.CO(co), .S(s), .A(a), .B(b), .CI(ci) );
endmodule
![[Up: CS_byte g03]](v2html-up.gif)
![[Up: CS_byte g13]](v2html-up.gif)
![[Up: CS_byte g23]](v2html-up.gif)
![[Up: CS_byte g33]](v2html-up.gif)
![[Up: CS_byte g43]](v2html-up.gif)
![[Up: CS_byte g53]](v2html-up.gif)
![[Up: CS_byte g63]](v2html-up.gif)
![[Up: CS_byte g73]](v2html-up.gif)
module ME_ADD3_B
(a, b, ci, s, co);
input a
, b
, ci
;
output s
, co
;
JFAD1A u0 (.CO(co), .S(s), .A(a), .B(b), .CI(ci) );
endmodule
// comparators
module ME_COMP3
(a, b, z);
input [2:0] a
, b
;
output z
;
ACOMP3A u0 (.A0(a[0]), .A1(a[1]), .A2(a[2]),
.B0(b[0]), .B1(b[1]), .B2(b[2]), .O(z) );
endmodule
![[Up: rfrw_ctl cmp_wa_ra1]](v2html-up.gif)
![[Up: rfrw_ctl cmp_wa_ra2]](v2html-up.gif)
![[Up: rfrw_ctl cmp_wa_ra3_d]](v2html-up.gif)
![[Up: rfrw_ctl cmp_wa_ra3_e]](v2html-up.gif)
![[Up: fhold_ctl cmp_d_rd_e]](v2html-up.gif)
![[Up: chkdep_rd_src cmp_rd_rs1]](v2html-up.gif)
![[Up: chkdep_rd_src cmp_rd_rs2]](v2html-up.gif)
![[Up: chkdep_rd_all cmp_rd_rd]](v2html-up.gif)
![[Up: chkdep_rd_all cmp_rd_rs1]](v2html-up.gif)
module ME_COMP4
(a, b, z);
input [3:0] a
, b
;
output z
;
ACOMP4A u0 (.A0(a[0]), .A1(a[1]), .A2(a[2]), .A3(a[3]),
.B0(b[0]), .B1(b[1]), .B2(b[2]), .B3(b[3]), .O(z) );
endmodule
module ME_COMP5
(a, b, z);
input [4:0] a
, b
;
output z
;
ACOMP5A u0 (.A0(a[0]), .A1(a[1]), .A2(a[2]), .A3(a[3]), .A4(a[4]),
.B0(b[0]), .B1(b[1]), .B2(b[2]), .B3(b[3]), .B4(b[4]), .O(z) );
endmodule
// multiplexors
// Binary encoded muxes
![[Up: ShiftLeftCtl g20]](v2html-up.gif)
![[Up: ShiftLeftCtl g21]](v2html-up.gif)
![[Up: ShiftLeftCtl g22]](v2html-up.gif)
![[Up: acell10 g19]](v2html-up.gif)
![[Up: rfrw_ctl iu_hold_gate_12]](v2html-up.gif)
![[Up: rfrw_ctl iu_hold_gate_13]](v2html-up.gif)
![[Up: pproduct21 p1]](v2html-up.gif)
![[Up: pproduct21 p2]](v2html-up.gif)
![[Up: pproduct23 p0]](v2html-up.gif)
![[Up: pproduct23 p1]](v2html-up.gif)
![[Up: pproduct24 p1]](v2html-up.gif)
![[Up: pproduct24 p2]](v2html-up.gif)
![[Up: pproduct25 p1]](v2html-up.gif)
![[Up: pproduct25 p2]](v2html-up.gif)
![[Up: pproduct26 p1]](v2html-up.gif)
![[Up: pproduct26 p2]](v2html-up.gif)
![[Up: AdderLSBlog g15]](v2html-up.gif)
![[Up: SignLogic saop]](v2html-up.gif)
![[Up: StickyPairNCI g34]](v2html-up.gif)
![[Up: ME_MUX8B m2]](v2html-up.gif)
![[Up: ExpAdderLSB g12]](v2html-up.gif)
![[Up: pproduct52_27 p1]](v2html-up.gif)
![[Up: pproduct52_27 p2]](v2html-up.gif)
![[Up: pproduct52_27 p3]](v2html-up.gif)
![[Up: DivLog qb1m]](v2html-up.gif)
![[Up: CregLoadCtl fg1]](v2html-up.gif)
module ME_MUX2B
(s, a, b, z);
input s
, a
, b
;
output z
;
AMUX2A u0 (.O(z), .A(a), .B(b), .S(s) );
endmodule
![[Up: SignLogic asmp]](v2html-up.gif)
module ME_MUX2B_B
(s, a, b, z);
input s
, a
, b
;
output z
;
AMUX2A u0 (.O(z), .A(a), .B(b), .S(s) );
endmodule
![[Up: CondMux vc_1]](v2html-up.gif)
![[Up: CondMux vc_4]](v2html-up.gif)
![[Up: acell10 g12]](v2html-up.gif)
![[Up: acell10 g25]](v2html-up.gif)
![[Up: acell10 g26]](v2html-up.gif)
![[Up: acell16 g12]](v2html-up.gif)
![[Up: acell16 g13]](v2html-up.gif)
![[Up: acell16 g14]](v2html-up.gif)
![[Up: acell16 g25]](v2html-up.gif)
![[Up: StickyPairNC g28]](v2html-up.gif)
![[Up: twosch m4]](v2html-up.gif)
![[Up: acell4a g17]](v2html-up.gif)
![[Up: acell4a g20]](v2html-up.gif)
![[Up: acell4a g24]](v2html-up.gif)
![[Up: acell4a g25]](v2html-up.gif)
![[Up: CS_byte g01]](v2html-up.gif)
![[Up: CS_byte g11]](v2html-up.gif)
![[Up: CS_byte g21]](v2html-up.gif)
![[Up: CS_byte g31]](v2html-up.gif)
![[Up: CS_byte g41]](v2html-up.gif)
![[Up: CS_byte g51]](v2html-up.gif)
![[Up: CS_byte g61]](v2html-up.gif)
![[Up: CS_byte g71]](v2html-up.gif)
![[Up: FREG_5bit n0]](v2html-up.gif)
![[Up: AdderLSBlog g16]](v2html-up.gif)
![[Up: FREG_S_5bit n0]](v2html-up.gif)
![[Up: acell4 g18]](v2html-up.gif)
![[Up: acell4 g20]](v2html-up.gif)
![[Up: acell4 g24]](v2html-up.gif)
![[Up: acell4 g25]](v2html-up.gif)
![[Up: CS_bit g11]](v2html-up.gif)
... (truncated)
module ME_NMUX2B
(s, a, b, z); // inverting mux
input s
, a
, b
;
output z
;
JMUX2A u0 (.O(z), .A(a), .B(b), .S(s) );
endmodule
![[Up: CondMux sp_2]](v2html-up.gif)
![[Up: CondMux sp_3]](v2html-up.gif)
![[Up: acell10 g17]](v2html-up.gif)
![[Up: acell16 g18]](v2html-up.gif)
![[Up: acell16 g20]](v2html-up.gif)
![[Up: acell16 g26]](v2html-up.gif)
![[Up: acell1a g4]](v2html-up.gif)
![[Up: StickyPairNC g34]](v2html-up.gif)
![[Up: twosch_top m4]](v2html-up.gif)
![[Up: BregLoadCtl alcn0]](v2html-up.gif)
![[Up: acell4a g12]](v2html-up.gif)
![[Up: acell4a g13]](v2html-up.gif)
![[Up: acell4a g14]](v2html-up.gif)
![[Up: FREG_8bit_s sm0]](v2html-up.gif)
![[Up: AdderLSBlog g12]](v2html-up.gif)
![[Up: acell1 g4]](v2html-up.gif)
![[Up: acell4 g12]](v2html-up.gif)
![[Up: acell4 g13]](v2html-up.gif)
![[Up: acell4 g14]](v2html-up.gif)
![[Up: SignLogic asm]](v2html-up.gif)
![[Up: SignLogic asmv]](v2html-up.gif)
![[Up: ExpShifter sm4]](v2html-up.gif)
![[Up: ExpShifter sm3]](v2html-up.gif)
![[Up: ExpShifter sm2]](v2html-up.gif)
![[Up: ExpShifter sm1]](v2html-up.gif)
![[Up: ExpShifter sm0]](v2html-up.gif)
![[Up: adder13 g13]](v2html-up.gif)
![[Up: adder13 g15]](v2html-up.gif)
![[Up: adder13 g18]](v2html-up.gif)
![[Up: AregLoadCtl alcn0]](v2html-up.gif)
![[Up: PreventSwapCtl psg6]](v2html-up.gif)
... (truncated)
module ME_NMUX2B_B
(s, a, b, z); // inverting mux
input s
, a
, b
;
output z
;
JMUX2A u0 (.O(z), .A(a), .B(b), .S(s) );
endmodule
![[Up: ShiftDec mu1]](v2html-up.gif)
![[Up: ShiftDec mu0]](v2html-up.gif)
module ME_NMUX2BA
(nota, a, d0, d1, notX);
// A very important special case
// use with care as A being on at the same time as notA burns power.
// note the order of the inputs which is choosen so that this is compatable
// with an NMUX2 although the behaviour is only the same if both a driven
// from true and inverse of a signal
input a
, nota
, d0
, d1
;
output notX
;
JD22A i (.O(notX), .A1(nota), .A2(d0), .B1(a), .B2(d1) );
endmodule
module ME_NMUX2BA_B
(nota, a, d0, d1, notX);
// A very important special case
// use with care as A being on at the same time as notA burns power.
// note the order of the inputs which is choosen so that this is compatable
// with an NMUX2 although the behaviour is only the same if both a driven
// from true and inverse of a signal
input a
, nota
, d0
, d1
;
output notX
;
JD22A i (.O(notX), .A1(nota), .A2(d0), .B1(a), .B2(d1) );
endmodule
![[Up: ME_MUX_4Bbyte m0]](v2html-up.gif)
![[Up: ME_MUX_4Bbyte m1]](v2html-up.gif)
![[Up: ME_MUX_4Bbyte m2]](v2html-up.gif)
![[Up: ME_MUX_4Bbyte m3]](v2html-up.gif)
![[Up: ME_MUX_4Bbyte m4]](v2html-up.gif)
![[Up: ME_MUX_4Bbyte m5]](v2html-up.gif)
![[Up: ME_MUX_4Bbyte m6]](v2html-up.gif)
![[Up: ME_MUX_4Bbyte m7]](v2html-up.gif)
![[Up: fp_qst fq_rs1_0_mux]](v2html-up.gif)
![[Up: fp_qst fq_rs2_0_mux]](v2html-up.gif)
![[Up: fp_qst src_size_mux]](v2html-up.gif)
![[Up: CondMux vx_3]](v2html-up.gif)
![[Up: CondMux vx_2]](v2html-up.gif)
![[Up: FREG_5bit m0]](v2html-up.gif)
![[Up: FREG_S_5bit m0]](v2html-up.gif)
![[Up: SignLogic msc0]](v2html-up.gif)
![[Up: ME_NMUX5B m2]](v2html-up.gif)
![[Up: ME_MUX_4B_10 m16]](v2html-up.gif)
![[Up: ME_MUX_4B_10 m15]](v2html-up.gif)
![[Up: ME_MUX_4B_13 m16]](v2html-up.gif)
![[Up: ME_MUX_4B_13 m15]](v2html-up.gif)
![[Up: ME_MUX_4B_13 m17]](v2html-up.gif)
![[Up: ME_MUX_4B_13 m18]](v2html-up.gif)
![[Up: ME_MUX_4B_13 m19]](v2html-up.gif)
![[Up: ME_MUX8B m0]](v2html-up.gif)
![[Up: ME_MUX8B m1]](v2html-up.gif)
![[Up: FREG_4Bit n0]](v2html-up.gif)
![[Up: ME_MUX_4B_4 m0]](v2html-up.gif)
![[Up: ME_MUX_4B_4 m1]](v2html-up.gif)
![[Up: ME_MUX_4B_4 m2]](v2html-up.gif)
![[Up: ME_MUX_4B_4 m3]](v2html-up.gif)
... (truncated)
module ME_MUX4B
(a, b, d0, d1, d2, d3, z);
input a
, b
, d0
, d1
, d2
, d3
;
output z
;
// note A is least significant select line.
// A B Selected
// 00 d0
// 10 d1
// 01 d2
// 11 d3
AMUX4A m0 (.S0(a), .S1(b), .I1(d0), .I2(d1), .I3(d2), .I4(d3), .O(z) );
endmodule
![[Up: ME_MUX8B_B m0]](v2html-up.gif)
module ME_MUX4B_B
(a, b, d0, d1, d2, d3, z);
input a
, b
, d0
, d1
, d2
, d3
;
output z
;
// note A is least significant select line.
// A B Selected
// 00 d0
// 10 d1
// 01 d2
// 11 d3
AMUX4A m0 (.S0(a), .S1(b), .I1(d0), .I2(d1), .I3(d2), .I4(d3), .O(z) );
endmodule
module ME_NMUX5B
(A, B, C, D0, D1, D2, D3, D4, notXout);
input A
, B
, C
, D0
, D1
, D2
, D3
, D4
;
output notXout
;
// note A is least significant select line.
// A B C Selected
// 000 d0
// 100 d1
// 010 d2
// 110 d3
// ??1 d4
ME_MUX4B m2 (A, B, D0, D1, D2, D3, T0
);
ME_NMUX2B m1 (C, T0, D4, notXout) ;
endmodule
module ME_MUX8B
(a, b, c, d0, d1, d2, d3, d4, d5, d6, d7, f);
input a
, b
, c
, d0
, d1
, d2
, d3
, d4
, d5
, d6
, d7
;
output f
;
// note A is least significant select line.
ME_MUX4B m0 (a, b, d0, d1, d2, d3, z0
);
ME_MUX4B m1 (a, b, d4, d5, d6, d7, z1
);
ME_MUX2B m2 (c, z0, z1, f);
endmodule
![[Up: FREG_8bit_s n0]](v2html-up.gif)
module ME_MUX8B_B
(a, b, c, d0, d1, d2, d3, d4, d5, d6, d7, f);
input a
, b
, c
, d0
, d1
, d2
, d3
, d4
, d5
, d6
, d7
;
output f
;
// note A is least significant select line.
ME_MUX4B_B m0 (a, b, d0, d1, d2, d3, z0
);
ME_MUX4B_B m1 (a, b, d4, d5, d6, d7, z1
);
ME_MUX2B_B m2 (c, z0, z1, f);
endmodule
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... (truncated)
module ME_MUX_2Bbit
( notA, A, D0, D1, Xout ) ;
input notA
, A
;
input D0
, D1
;
output Xout
;
JDB22A g0 ( .A1(notA), .A2(D0), .B1(A), .B2(D1), .O(Xout) );
endmodule
![[Up: ME_MUX_2B_B_13 m11]](v2html-up.gif)
![[Up: ME_MUX_2B_B_13 m12]](v2html-up.gif)
![[Up: ME_MUX_2B_B_13 m13]](v2html-up.gif)
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![[Up: ME_MUX_2B_B_13 m15]](v2html-up.gif)
![[Up: ME_MUX_2B_Bbyte g10]](v2html-up.gif)
![[Up: ME_MUX_2B_Bbyte g11]](v2html-up.gif)
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module ME_MUX_2B_Bbit
( notA, A, D0, D1, Xout ) ;
input notA
, A
;
input D0
, D1
;
output Xout
;
JDB22A g0 ( .A1(notA), .A2(D0), .B1(A), .B2(D1), .O(Xout) );
endmodule
![[Up: ME_NMUX_2B_57 m17]](v2html-up.gif)
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![[Up: ME_NMUX_2Bbyte g16]](v2html-up.gif)
module ME_NMUX_2Bbit
( notA, A, D0, D1, Xout ) ;
input notA
, A
;
input D0
, D1
;
output Xout
;
ME_NMUX2BA_B g0 ( .nota(notA), .a(A), .d0(D0), .d1(D1), .notX(Xout) );
endmodule
![[Up: ME_MUX_2B_B_13 m10]](v2html-up.gif)
![[Up: ME_MUX_2B_B_58 m10]](v2html-up.gif)
![[Up: ME_MUX_2B_B_58 m11]](v2html-up.gif)
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![[Up: ME_MUX_2B_B_58 m15]](v2html-up.gif)
module ME_MUX_2B_Bbyte
( notA, A, D0, D1, Xout ) ;
input notA
, A
;
input [7:0] D0
, D1
;
output [7:0] Xout
;
ME_MUX_2B_Bbit g10 ( notA, A, D0[0], D1[0], Xout[0] );
ME_MUX_2B_Bbit g11 ( notA, A, D0[1], D1[1], Xout[1] );
ME_MUX_2B_Bbit g12 ( notA, A, D0[2], D1[2], Xout[2] );
ME_MUX_2B_Bbit g13 ( notA, A, D0[3], D1[3], Xout[3] );
ME_MUX_2B_Bbit g14 ( notA, A, D0[4], D1[4], Xout[4] );
ME_MUX_2B_Bbit g15 ( notA, A, D0[5], D1[5], Xout[5] );
ME_MUX_2B_Bbit g16 ( notA, A, D0[6], D1[6], Xout[6] );
ME_MUX_2B_Bbit g17 ( notA, A, D0[7], D1[7], Xout[7] );
endmodule
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![[Up: ME_MUX_2B_64 m17]](v2html-up.gif)
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... (truncated)
module ME_MUX_2Bbyte
( notA, A, D0, D1, Xout ) ;
input notA
, A
;
input [7:0] D0
, D1
;
output [7:0] Xout
;
ME_MUX_2Bbit g10 ( notA, A, D0[0], D1[0], Xout[0] );
ME_MUX_2Bbit g11 ( notA, A, D0[1], D1[1], Xout[1] );
ME_MUX_2Bbit g12 ( notA, A, D0[2], D1[2], Xout[2] );
ME_MUX_2Bbit g13 ( notA, A, D0[3], D1[3], Xout[3] );
ME_MUX_2Bbit g14 ( notA, A, D0[4], D1[4], Xout[4] );
ME_MUX_2Bbit g15 ( notA, A, D0[5], D1[5], Xout[5] );
ME_MUX_2Bbit g16 ( notA, A, D0[6], D1[6], Xout[6] );
ME_MUX_2Bbit g17 ( notA, A, D0[7], D1[7], Xout[7] );
endmodule
![[Up: ME_NMUX_2B_57 m10]](v2html-up.gif)
![[Up: ME_NMUX_2B_57 m11]](v2html-up.gif)
![[Up: ME_NMUX_2B_57 m12]](v2html-up.gif)
![[Up: ME_NMUX_2B_57 m13]](v2html-up.gif)
![[Up: ME_NMUX_2B_57 m14]](v2html-up.gif)
![[Up: ME_NMUX_2B_57 m15]](v2html-up.gif)
![[Up: ME_NMUX_2B_57 m16]](v2html-up.gif)
![[Up: ME_NMUX_2B_58 m10]](v2html-up.gif)
![[Up: ME_NMUX_2B_58 m11]](v2html-up.gif)
![[Up: ME_NMUX_2B_58 m12]](v2html-up.gif)
![[Up: ME_NMUX_2B_58 m13]](v2html-up.gif)
![[Up: ME_NMUX_2B_58 m14]](v2html-up.gif)
![[Up: ME_NMUX_2B_58 m15]](v2html-up.gif)
![[Up: ME_NMUX_2B_58 m16]](v2html-up.gif)
module ME_NMUX_2Bbyte
( notA, A, D0, D1, Xout ) ;
input notA
, A
;
input [7:0] D0
, D1
;
output [7:0] Xout
;
ME_NMUX_2Bbit g10 ( notA, A, D0[0], D1[0], Xout[0] );
This page: |
Created: | Thu Aug 19 12:00:55 1999 |
| From: |
../../../sparc_v8/lib/rtl/me_cells.v
|