/******************************************************************************/ 
/*                                                                            */ 
/* Copyright (c) 1999 Sun Microsystems, Inc. All rights reserved.             */ 
/*                                                                            */ 
/* The contents of this file are subject to the current version of the Sun    */ 
/* Community Source License, microSPARCII ("the License"). You may not use    */ 
/* this file except in compliance with the License.  You may obtain a copy    */ 
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/* obligations, and limitations governing use of the contents of this file.   */ 
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/* these intellectual property rights may include one or more U.S. patents,   */ 
/* foreign patents, or pending applications.                                  */ 
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/* Solaris, Java and all Java-based trademarks and logos are trademarks or    */ 
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/* other countries. microSPARC is a trademark or registered trademark of      */ 
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/*                                                                            */ 
/******************************************************************************/ 
/***************************************************************************
****************************************************************************
***
***  Program File:  @(#)me_cells.v
***
****************************************************************************
****************************************************************************/

/*
PRIMATIVES

Latches
Combinational logic gates
Multiplexors
Pads
Clock buffers

MACROS -- use seperate file macros.v

Registers
Wide multiplexors
Bus drivers

Shifters
Alus
Adders

Rams
Roms

*/

/* Latches
ME_LD1  simple d latch, active LOW clock
ME_FD1  fimple ff active on positive clock edge
ME_FD1E FD2 with a data load enable
ME_FD1E2 FD2 with two data inputs, each with is own enable.
FJK1 JK flip flop, pos edge load.
FJK2 JK flip flop, pos edge load, with active low clear.
*/

/* logic Gates
NAND{n} n input nand gate
NOR{n}  n input nor gate
AND{n}  n input and gate
OR{n}   n input or gate
ME_INVA    invertor
ME_BUFF    buffer
ME_DELBUFF buffer with approx 3ns delay
ME_TSBUFF  tristate buffer
ME_XOR2    2 input xor gate
ME_XNOR2   2 input xnor
ME_ADD2    half adder
ME_ADD3    full adder
*/

/* Matrix Gates
ME_AnOmI   And-Or-Invert gates
ME_OnAmI   Or-And-Invert gates
*/

/*  Multiplexors/selectors
MUX{n}   n input multiplexor with seperate selectors
NMUX{n}  n input inverting multiplexor with seperate selectors

MUX{n)B  binary coded selectors.
NMUX{n)B binary coded selectors, inverting

ME_NMUX2BA  as NMUX2B except you must supply true and false of control inputs
*/

/* Pads */


/* MACROS */

/* registers
DREG_{x}_{y} x bit wide register with y inputs. transparent when clock high
FREG_{x}_{y} x bit wide register with y inputs. edge trigger on posedge strobe
MUX_{x}_{y}  x bit wide multiplexor with y inputs
*/

/* function blocks
ALU_{x}      x bit wide ALU
ME_ADD_{x}      x bit wide add/subtract
*/

/* roms and roms
ME_ROM_{x}_{y}  x bit wide rom with y address bits
ME_RAM_{x}_{y}  x bit wide ram with y address bits
ME_RAM3_{x}_{y} x bit wide 3 port ram with y address bits
*/

/* Actual modules */

... (truncated)
module ME_FD1 (cp, d, q, qn);
   input d, cp;
   output q, qn ;

//   N1Z000 gnd(GND);
//   ASFFA dff (.Q(q), .XQ(qn), .D(d), .SM(GND), .SI(GND),  .CK(cp));

   Mflipflop_noop dff (.out(q), .in(d), .clock(cp) );
   assign qn = ~q;

endmodule


module ME_FD1_B (cp, d, q, qn);
   input d, cp;
   output q, qn ;

//   N1Z000 gnd(GND);
//   ASFFA dff (.Q(q), .XQ(qn), .D(d), .SM(GND), .SI(GND),  .CK(cp));

   Mflipflop_noop dff (.out(q), .in(d), .clock(cp) );
   assign qn = ~q;

endmodule


module ME_FD1P (cp, d, q, qn);	// should be a high drive version of ME_FD1;
   input d, cp;			// for simulation, they are the same.
   output q, qn ;

//   N1Z000 gnd(GND);
//   ASFFA dff (.Q(q), .XQ(qn), .D(d), .SM(GND), .SI(GND),  .CK(cp));

   Mflipflop_noop dff (.out(q), .in(d), .clock(cp) );
   assign qn = ~q;

endmodule

... (truncated)
module ME_FDS2LP (d, cp, cr, ld, q, qn);
// ld is active high, cr is active low
   input d, cp, cr, ld;
   output q, qn;
   
//    N1Z000 gnd(GND);
//    wire hold;
//    JINVA i0  ( .O(hold), .A(ld) );
//    ASFFRHA dff ( .Q(q), .XQ(qn), .D(d), .SM(GND), .SI(GND),
//		 .H(hold), .R(cr), .CK(cp) ) ;

   wire load_l;
   assign load_l = ~ld;
   Mflipflop_rh dff (.out(q), .in(d), .enable_l(load_l), .reset_l(cr), .clock(cp));
   assign qn = ~q;

endmodule


module ME_FD1E (cp, te, d, q, qn);
// like FD1 but with enable 
// note enable is active high
   input d, cp, te;
   output q, qn ;

//   N1Z000 gnd(GND);
//   wire hold;
//   JINVA i0  ( .O(hold), .A(te) );
//   ASFFHA  dff ( .Q(q), .XQ(qn), .D(d), .SM(GND), .SI(GND),
//		.H(hold), .CK(cp)) ;

   wire load_l;
   assign load_l = ~te;
   Mflipflop dff (.out(q), .in(d), .clock(cp), .enable_l(load_l));
   assign qn = ~q;

endmodule


module ME_FD1E_B (cp, te, d, q, qn);
// like FD1 but with enable 
// note enable is active high
   input d, cp, te;
   output q, qn ;

//   N1Z000 gnd(GND);
//   wire hold;
//   JINVA i0 ( .O(hold), .A(te) );
//   ASFFHA dff ( .Q(q), .XQ(qn), .D(d), .SM(GND), .SI(GND),
//		.H(hold), .CK(cp)) ;

   wire load_l;
   assign load_l = ~te;
   Mflipflop dff (.out(q), .in(d), .clock(cp), .enable_l(load_l));
   assign qn = ~q;

endmodule


module ME_FD1R (d, cp, cr, q, qn);
// CR (reset) is active low
   input d, cp, cr;
   output q, qn;
   
//    N1Z000 gnd(GND);
//    ASFFRA dff  ( .Q(q), .XQ(qn), .D(d), .SM(GND), .SI(GND),
//		 .R(cr), .CK(cp) ) ;

   Mflipflop_r dff (.out(q), .in(d), .reset_l(cr), .clock(cp));
   assign qn = ~q;

endmodule

// Logic Gates
... (truncated)
module ME_INV_A (a, x); // Meanest gate
   input a;
   output x;
   JINVA i (.O(x), .A(a) );
endmodule

... (truncated)
module ME_INVA (a, x);
   input a;
   output x;
   JINVA i (.O(x), .A(a) );
endmodule

... (truncated)
module ME_INV_B (a, x);
   input a;
   output x;
   JINVB i (.O(x), .A(a) );
endmodule

... (truncated)
module ME_INV_C (a, x);
   input a;
   output x;
   JINVC i (.O(x), .A(a) );
endmodule


module ME_INV_D (a, x);
   input a;
   output x;
   JINVD i (.O(x), .A(a) );
endmodule


module ME_INV_A_10 (A, Z);
   input [9:0] A;
   output [9:0] Z;

JINVA g0 (.O(Z[0]), .A(A[0]) );
JINVA g1 (.O(Z[1]), .A(A[1]) );
JINVA g2 (.O(Z[2]), .A(A[2]) );
JINVA g3 (.O(Z[3]), .A(A[3]) );
JINVA g4 (.O(Z[4]), .A(A[4]) );
JINVA g5 (.O(Z[5]), .A(A[5]) );
JINVA g6 (.O(Z[6]), .A(A[6]) );
JINVA g7 (.O(Z[7]), .A(A[7]) );
JINVA g8 (.O(Z[8]), .A(A[8]) );
JINVA g9 (.O(Z[9]), .A(A[9]) );

endmodule


module ME_INV_A_58 (A, Z);
   input [57:0] A;
   output [57:0] Z;

   ME_INV_A_10 h0 (A[9:0], Z[9:0]);
   ME_INV_A_10 h2 (A[19:10], Z[19:10]);
   ME_INV_A_10 h3 (A[29:20], Z[29:20]);
   ME_INV_A_10 h4 (A[39:30], Z[39:30]);
   ME_INV_A_10 h5 (A[49:40], Z[49:40]);
   ME_INV_A    g0 (A[50], Z[50]);
   ME_INV_A    g1 (A[51], Z[51]);
   ME_INV_A    g2 (A[52], Z[52]);
   ME_INV_A    g3 (A[53], Z[53]);
   ME_INV_A    g4 (A[54], Z[54]);
   ME_INV_A    g5 (A[55], Z[55]);
   ME_INV_A    g6 (A[56], Z[56]);
   ME_INV_A    g7 (A[57], Z[57]);

endmodule


module ME_BUFF (a, x);
   input a;
   output x;
   JBUFC i (.O(x), .A(a) );
endmodule


module ME_BUF_B (a, x); // Same as ME_BUFF
   input a;
   output x;
   JBUFD i (.O(x), .A(a) );
endmodule

... (truncated)
module ME_BUF_C (a, x); // Same as ME_BUFF
   input a;
   output x;
   JBUFD i (.O(x), .A(a) );
endmodule


module ME_BUF_D (a, x); // Same as ME_BUFF
   input a;
   output x;
   JBUFE i (.O(x), .A(a) );
endmodule

module ME_BUF3_4 ( a, x );
   input [3:0] a;
   output [3:0] x;

   ME_BUF_C i0 (a[0], x[0]);
   ME_BUF_C i1 (a[1], x[1]);
   ME_BUF_C i2 (a[2], x[2]);
   ME_BUF_C i3 (a[3], x[3]);
endmodule


module ME_BUF32_C ( a, x );
   input  [31:0] a;
   output [31:0] x;
   JBUFC i0  (.O(x[0]), .A(a[0]) );
   JBUFC i1  (.O(x[1]), .A(a[1]) );
   JBUFC i2  (.O(x[2]), .A(a[2]) );
   JBUFC i3  (.O(x[3]), .A(a[3]) );
   JBUFC i4  (.O(x[4]), .A(a[4]) );
   JBUFC i5  (.O(x[5]), .A(a[5]) );
   JBUFC i6  (.O(x[6]), .A(a[6]) );
   JBUFC i7  (.O(x[7]), .A(a[7]) );
   JBUFC i8  (.O(x[8]), .A(a[8]) );
   JBUFC i9  (.O(x[9]), .A(a[9]) );
   JBUFC i10 (.O(x[10]), .A(a[10]) );
   JBUFC i11 (.O(x[11]), .A(a[11]) );
   JBUFC i12 (.O(x[12]), .A(a[12]) );
   JBUFC i13 (.O(x[13]), .A(a[13]) );
   JBUFC i14 (.O(x[14]), .A(a[14]) );
   JBUFC i15 (.O(x[15]), .A(a[15]) );
   JBUFC i16 (.O(x[16]), .A(a[16]) );
   JBUFC i17 (.O(x[17]), .A(a[17]) );
   JBUFC i18 (.O(x[18]), .A(a[18]) );
   JBUFC i19 (.O(x[19]), .A(a[19]) );
   JBUFC i20 (.O(x[20]), .A(a[20]) );
   JBUFC i21 (.O(x[21]), .A(a[21]) );
   JBUFC i22 (.O(x[22]), .A(a[22]) );
   JBUFC i23 (.O(x[23]), .A(a[23]) );
   JBUFC i24 (.O(x[24]), .A(a[24]) );
   JBUFC i25 (.O(x[25]), .A(a[25]) );
   JBUFC i26 (.O(x[26]), .A(a[26]) );
   JBUFC i27 (.O(x[27]), .A(a[27]) );
   JBUFC i28 (.O(x[28]), .A(a[28]) );
   JBUFC i29 (.O(x[29]), .A(a[29]) );
   JBUFC i30 (.O(x[30]), .A(a[30]) );
   JBUFC i31 (.O(x[31]), .A(a[31]) );
endmodule

... (truncated)
module ME_NAND2 (a, b, z);
   input a, b;
   output z;
   JNAND2A i (.O(z), .A1(a), .A2(b) );
endmodule


module ME_NAND2_B (a, b, z);
   input a, b;
   output z;
   JNAND2B i (.O(z), .A1(a), .A2(b) );
endmodule

... (truncated)
module ME_NAND3 (a, b, c, z);
   input a, b, c;
   output z ;
   JNAND3A i (.O(z), .A1(a), .A2(b), .A3(c) );
endmodule


module ME_NAND3_B (a, b, c, z);
   input a, b, c;
   output z ;
   JNAND3B i (.O(z), .A1(a), .A2(b), .A3(c) );
endmodule


module ME_NAND4 (a, b, c, d, z);
   input a, b, c, d;
   output z ;
   JNAND4A i (.O(z), .A1(a), .A2(b), .A3(c), .A4(d) );
endmodule

module ME_NAND5 (a, b, c, d, e, z);
   input a, b, c, d, e;
   output z ;
   ANAND5C i (.O(z), .A1(a), .A2(b), .A3(c), .A4(d), .A5(e) );
endmodule


module ME_NAND6_B (a, b, c, d, e, f, z);
   input a, b, c, d, e, f;
   output z ;
   JNAND6C i (.O(z), .A1(a), .A2(b), .A3(c), .A4(d), .A5(e), .A6(f) );
endmodule

module ME_NAND8 (a, b, c, d, e, f, g, h, z);
   input a, b, c, d, e, f, g, h ;
   output z ;
   JNAND8C i (.O(z), .A1(a), .A2(b), .A3(c), .A4(d), .A5(e), .A6(f),
		.A7(g), .A8(h) );
endmodule


module ME_NAND8_B (a, b, c, d, e, f, g, h, z);
   input a, b, c, d, e, f, g, h ;
   output z ;
   JNAND8C i (.O(z), .A1(a), .A2(b), .A3(c), .A4(d), .A5(e), .A6(f),
		.A7(g), .A8(h) );
endmodule

// AND gates
... (truncated)
module ME_AND2 (a, b, z);
   input a, b;
   output z;
   JAND2B i (.O(z), .A1(a), .A2(b) );
endmodule


module ME_AND2_B (a, b, z);
   input a, b;
   output z;
   JAND2B i (.O(z), .A1(a), .A2(b) );
endmodule


module ME_AND3 (a, b, c, z);
   input a, b, c;
   output z;
   JAND3B i (.O(z), .A1(a), .A2(b), .A3(c) );
endmodule


module ME_AND3_B (a, b, c, z);
   input a, b, c;
   output z;
   JAND3B i (.O(z), .A1(a), .A2(b), .A3(c) );
endmodule


module ME_AND4 (a, b, c, d, z);
   input a, b, c, d;
   output z;
   JAND4B i (.O(z), .A1(a), .A2(b), .A3(c), .A4(d) );
endmodule


module ME_AND4_B (a, b, c, d, z);
   input a, b, c, d;
   output z;
   JAND4B i (.O(z), .A1(a), .A2(b), .A3(c), .A4(d) );
endmodule

module ME_AND7 ( a1, a2, a3, a4, a5, a6, a7, z );
   input a1, a2, a3, a4, a5, a6, a7 ;
   output z ;
   wire x1, x2;
   JNAND3A i0 (.O(x1), .A1(a1), .A2(a2), .A3(a3) );
   JNAND4A i1 (.O(x2), .A1(a4), .A2(a5), .A3(a6), .A4(a7) );
   JNOR2A i2 (.O(z), .A1(x1), .A2(x2) );
endmodule


module ME_AND8 (a, b, c, d, e, f, g, h, z);
   input a, b, c, d, e, f, g, h ;
   output z ;
   JAND8B i (.O(z), .A1(a), .A2(b), .A3(c), .A4(d), .A5(e), .A6(f),
		.A7(g), .A8(h) );
endmodule

// nor gates

module ME_NOR2 (a, b, z);
   input a, b ;
   output z;
   JNOR2A i (.O(z), .A1(a), .A2(b) );
endmodule


module ME_NOR2_B (a, b, z);
   input a, b ;
   output z;
   JNOR2C i (.O(z), .A1(a), .A2(b) );
endmodule


module ME_NOR2_D (a, b, z);
   input a, b ;
   output z;
   JNOR2D i (.O(z), .A1(a), .A2(b) );
endmodule


module ME_NOR3 (a, b, c, z);
   input a, b, c ;
   output z;
   JNOR3C i (.O(z), .A1(a), .A2(b), .A3(c) );
endmodule


module ME_NOR4 (a, b, c, d, z);
   input a, b, c, d ;
   output z;
   JNOR4B i (.O(z), .A1(a), .A2(b), .A3(c), .A4(d) );
endmodule

module ME_NOR6_B (a, b, c, d, e, f, z);
   input a, b, c, d, e, f ;
   output z;
   JNOR6C i (.O(z), .A1(a), .A2(b), .A3(c), .A4(d), .A5(e), .A6(f) );
endmodule


module ME_OR2 (a, b, z);
   input a, b ;
   output z;
   JOR2B i (.O(z), .A1(a), .A2(b) );
endmodule

... (truncated)
module ME_OR2_B (a, b, z);
   input a, b ;
   output z;
   JOR2B i (.O(z), .A1(a), .A2(b) );
endmodule


module ME_OR3 (a, b, c, z);
   input a, b, c ;
   output z;
   JOR3B i (.O(z), .A1(a), .A2(b), .A3(c) );
endmodule


module ME_OR3_B (a, b, c, z);
   input a, b, c ;
   output z;
   JOR3B i (.O(z), .A1(a), .A2(b), .A3(c) );
endmodule


module ME_OR4 (a, b, c, d, z);
   input a, b, c, d ;
   output z;
   JOR4B i (.O(z), .A1(a), .A2(b), .A3(c), .A4(d) );
endmodule

module ME_OR6 (a, b, c, d, e, f, X);
   input a, b, c, d, e, f ;
   output X ;
   JOR6B i (.O(X), .A1(a), .A2(b), .A3(c), .A4(d), .A5(e), .A6(f) );
endmodule


module ME_OR8 (a, b, c, d, e, f, g, h, X);
   input a, b, c, d, e, f, g, h ;
   output X ;
   JOR8B i (.O(X), .A1(a), .A2(b), .A3(c), .A4(d), .A5(e), .A6(f),
		.A7(g), .A8(h) );
endmodule


module ME_OR11 (a, b, c, d, e, f, g, h, i, j, k, X);
   input a, b, c, d, e, f, g, h, i, j, k;
   output X ;
   wire x0, x1;
   JNOR8C u0 (.O(x0), .A1(a), .A2(b), .A3(c), .A4(d), .A5(e), .A6(f),
		.A7(g), .A8(h) );
   JNOR3A u1 (.O(x1), .A1(i), .A2(j), .A3(k) );
   JNAND2A u2 (.O(X), .A1(x0), .A2(x1) );
endmodule

module ME_OR12 (a, b, c, d, e, f, g, h, i, j, k, l, X);
   input a, b, c, d, e, f, g, h, i, j, k, l;
   output X ;
   wire x0, x1;
   JNOR8C u0 (.O(x0), .A1(a), .A2(b), .A3(c), .A4(d), .A5(e), .A6(f),
		.A7(g), .A8(h) );
   JNOR4B u1 (.O(x1), .A1(i), .A2(j), .A3(k), .A4(l) );
   JNAND2A u2 (.O(X), .A1(x0), .A2(x1) );
endmodule

module ME_XNOR2 (a, b, z);
   input a, b;
   output z;
   JXNOR2A i (.O(z), .A1(a), .A2(b) );
endmodule


module ME_XNOR2_B (a, b, z);
   input a, b;
   output z;
   JXNOR2B i (.O(z), .A1(a), .A2(b) );
endmodule


module ME_XOR2 (a, b, z);
   input a, b;
   output z;
   JXOR2A i (.O(z), .A1(a), .A2(b) );
endmodule


module ME_XOR2_B (a, b, z);
   input a, b;
   output z;
   JXOR2B i (.O(z), .A1(a), .A2(b) );
endmodule


module ME_XOR3_B (a, b, c, z);
   input a, b, c;
   output z;
   JXOR3A i (.O(z), .A1(a), .A2(b), .A3(c) );
endmodule

// Matrix gates


module ME_A2O1_B (a, b, c, z);			// z = (a&b) | c
   input a, b, c;
   output z;
   JDB21A i (.O(z), .A1(a), .A2(b), .B(c) );
endmodule


module ME_AI2O1_C (a, b, c, z);			// z = (a & ~b) | c
   input a, b, c;
   output z;
   ADBI21C i (.O(z), .A1(a), .A2(b), .B(c) );
endmodule

module ME_AI2O1_D (a, b, c, z);			// z = (a & ~b) | c
   input a, b, c;
   output z;
   ADBI21D i (.O(z), .A1(a), .A2(b), .B(c) );
endmodule

module ME_A22O1_B (a1, a2, b1, b2, c, z);	// z = (a1&a2) | (b1&b2) | c;
   input a1, a2, b1, b2, c;
   output z;
   JDB122A i (.O(z), .A1(a1), .A2(a2), .B1(b1), .B2(b2), .C(c) );
endmodule


module ME_AI22O1_C (a1, a2, b1, b2, c, z);	// z= (a1 & ~a2) | (b1&b2) | c;
   input a1, a2, b1, b2, c;
   output z;
   ADBI122C i (.O(z), .A1(a1), .A2(a2), .B1(b1), .B2(b2), .C(c) );
endmodule

module ME_AI22O1_D (a1, a2, b1, b2, c, z);	// z= (a1 & ~a2) | (b1&b2) | c;
   input a1, a2, b1, b2, c;
   output z;
   ADBI122D i (.O(z), .A1(a1), .A2(a2), .B1(b1), .B2(b2), .C(c) );
endmodule


module ME_AI22O1_C_2 (a1, a2, b1, b2, c, z);
input [1:0] a1, a2, b1, b2, c;
output [1:0] z;

   ADBI122C u0 (.O(z[0]), .A1(a1[0]), .A2(a2[0]), .B1(b1[0]), .B2(b2[0]),
		.C(c[0]) );
   ADBI122C u1 (.O(z[1]), .A1(a1[1]), .A2(a2[1]), .B1(b1[1]), .B2(b2[1]),
		.C(c[1]) );
endmodule


module ME_AI22O1_C_5 (a1, a2, b1, b2, c, z);
input [4:0] a1, a2, b1, b2, c;
output [4:0] z;

   ADBI122C u0 (.O(z[0]), .A1(a1[0]), .A2(a2[0]), .B1(b1[0]), .B2(b2[0]),
		.C(c[0]) );
   ADBI122C u1 (.O(z[1]), .A1(a1[1]), .A2(a2[1]), .B1(b1[1]), .B2(b2[1]),
		.C(c[1]) );
   ADBI122C u2 (.O(z[2]), .A1(a1[2]), .A2(a2[2]), .B1(b1[2]), .B2(b2[2]),
		.C(c[2]) );
   ADBI122C u3 (.O(z[3]), .A1(a1[3]), .A2(a2[3]), .B1(b1[3]), .B2(b2[3]),
		.C(c[3]) );
   ADBI122C u4 (.O(z[4]), .A1(a1[4]), .A2(a2[4]), .B1(b1[4]), .B2(b2[4]),
		.C(c[4]) );
endmodule

module ME_A2O2I (a, b, c, d, z);
   input a, b, c, d;
   output z;
   JD211A u1 (.O(z), .A1(a), .A2(b), .B1(c), .B2(d) );
endmodule

module ME_A2O2I_B (a, b, c, d, z);
   input a, b, c, d;
   output z;
   JD211A u1 (.O(z), .A1(a), .A2(b), .B1(c), .B2(d) );
endmodule

module ME_A22OI (a, b, c, d, z);
   input a, b, c, d;
   output z;
   JD22A i (.O(z), .A1(a), .A2(b), .B1(c), .B2(d) );
endmodule

module ME_A22OI_B (a, b, c, d, z);
   input a, b, c, d;
   output z;
   JD22A i (.O(z), .A1(a), .A2(b), .B1(c), .B2(d) );
endmodule

module ME_O2A2I (a, b, c, d, z);
   input a, b, c, d;
   output z;
   JG112A i (.O(z), .A1(a), .A2(b), .B1(c), .B2(d) );
endmodule

module ME_O2A2I_B (a, b, c, d, z);
   input a, b, c, d;
   output z;
   JG112A i (.O(z), .A1(a), .A2(b), .B1(c), .B2(d) );
endmodule

module ME_O22AI (a, b, c, d, z);
   input a, b, c, d;
   output z;
   JG22A i (.O(z), .A1(a), .A2(b), .B1(c), .B2(d) );
endmodule

module ME_O22AI_B (a, b, c, d, z);
   input a, b, c, d;
   output z;
   JG22A i (.O(z), .A1(a), .A2(b), .B1(c), .B2(d) );
endmodule

module ME_A2O1I (a, b, c, z);
   input a, b, c;
   output z;
   JD21A i (.O(z), .A1(a), .A2(b), .B(c) );
endmodule

module ME_A2O1I_B (a, b, c, z);
   input a, b, c;
   output z;
   JD21A i (.O(z), .A1(a), .A2(b), .B(c) );
endmodule


module ME_O2A1 (a, b, c, z);
   input a, b, c;
   output z;				// z = (a|b)&c
   JGB12A i (.O(z), .A1(a), .A2(b), .B(c) );
endmodule


module ME_O2A1_D (a, b, c, z);
   input a, b, c;
   output z;				// z = (a|b)&c
   AGB12D i (.O(z), .A1(a), .A2(b), .B(c) );
endmodule


module ME_O22A1 (a1, a2, b1, b2, c, z);
   input a1, a2, b1, b2, c;
   output z;				// z = (a1 | a2) & (b1 | b2) & c
   JGB221A i (.O(z), .A1(a1), .A2(a2), .B1(b1), .B2(b2), .C(c) );
endmodule


module ME_O2A1I (a, b, c, z);
   input a, b, c;
   output z;
   JG12A i (.O(z), .A1(a), .A2(b), .B(c) );
endmodule

module ME_O2A1I_B (a, b, c, z);
   input a, b, c;
   output z;
   JG12A i (.O(z), .A1(a), .A2(b), .B(c) );
endmodule

module ME_A222OI (a, b, c, d, e, f, z);
   input a, b, c, d, e, f;
   output z;
   JD222A i (.O(z), .A1(a), .A2(b), .B1(c), .B2(d), .C1(e), .C2(f) );
endmodule


module ME_A222OI_B (a, b, c, d, e, f, z);
   input a, b, c, d, e, f;
   output z;
   JD222A i (.O(z), .A1(a), .A2(b), .B1(c), .B2(d), .C1(e), .C2(f) );
endmodule

module ME_O2222AI (a, b, c, d, e, f, g, h, z);
   input a, b, c, d, e, f, g, h;
   output z;
   AG2222A i (.O(z), .A1(a), .A2(b), .B1(c), .B2(d), .C1(e), .C2(f),
		.D1(g), .D2(h) );
endmodule

module ME_O2222AI_B (a, b, c, d, e, f, g, h, z);
   input a, b, c, d, e, f, g, h;
   output z;
   AG2222A i (.O(z), .A1(a), .A2(b), .B1(c), .B2(d), .C1(e), .C2(f),
		.D1(g), .D2(h) );
endmodule


module ME_ADD2 (a, b, s, c);
   input a, b;
   output s,c;
   JHAD1A u0 (.CO(c), .S(s), .A(a), .B(b) );
endmodule

module ME_ADD3 (a, b, ci, s, co);
   input a, b, ci ;
   output  s, co ;
   JFAD1A u0 (.CO(co), .S(s), .A(a), .B(b), .CI(ci) );
endmodule


module ME_ADD3_B (a, b, ci, s, co);
   input a, b, ci ;
   output  s, co ;
   JFAD1A u0 (.CO(co), .S(s), .A(a), .B(b), .CI(ci) );
endmodule

// comparators

module ME_COMP3 (a, b, z);
   input [2:0] a, b;
   output z;
   ACOMP3A u0 (.A0(a[0]), .A1(a[1]), .A2(a[2]),
		.B0(b[0]), .B1(b[1]), .B2(b[2]), .O(z) );
endmodule


module ME_COMP4 (a, b, z);
   input [3:0] a, b;
   output z;
   ACOMP4A u0 (.A0(a[0]), .A1(a[1]), .A2(a[2]), .A3(a[3]),
		.B0(b[0]), .B1(b[1]), .B2(b[2]), .B3(b[3]), .O(z) );
endmodule

module ME_COMP5 (a, b, z);
   input [4:0] a, b;
   output z;
   ACOMP5A u0 (.A0(a[0]), .A1(a[1]), .A2(a[2]), .A3(a[3]), .A4(a[4]),
		.B0(b[0]), .B1(b[1]), .B2(b[2]), .B3(b[3]), .B4(b[4]), .O(z) );
endmodule


// multiplexors

// Binary encoded muxes

module ME_MUX2B (s, a, b, z);
   input s, a, b ;
   output z ;

   AMUX2A u0 (.O(z), .A(a), .B(b), .S(s) );
endmodule


module ME_MUX2B_B (s, a, b, z);
   input s, a, b ;
   output z ;

   AMUX2A u0 (.O(z), .A(a), .B(b), .S(s) );
endmodule

... (truncated)
module ME_NMUX2B (s, a, b, z);		// inverting mux
   input s, a, b ;
   output z ;

   JMUX2A u0 (.O(z), .A(a), .B(b), .S(s) );
endmodule

... (truncated)
module ME_NMUX2B_B (s, a, b, z);	// inverting mux
   input s, a, b ;
   output z ;

   JMUX2A u0 (.O(z), .A(a), .B(b), .S(s) );
endmodule


module ME_NMUX2BA (nota, a, d0, d1, notX);
// A very important special case 
// use with care as A being on at the same time as notA burns power.
// note the order of the inputs which is choosen so that this is compatable
// with an NMUX2  although the behaviour is only the same if both a driven
// from true and inverse of a signal
   input a, nota, d0, d1 ;
   output notX ;
   JD22A i (.O(notX), .A1(nota), .A2(d0), .B1(a), .B2(d1) );
endmodule


module ME_NMUX2BA_B (nota, a, d0, d1, notX);
// A very important special case 
// use with care as A being on at the same time as notA burns power.
// note the order of the inputs which is choosen so that this is compatable
// with an NMUX2  although the behaviour is only the same if both a driven
// from true and inverse of a signal
   input a, nota, d0, d1 ;
   output notX ;
   JD22A i (.O(notX), .A1(nota), .A2(d0), .B1(a), .B2(d1) );
endmodule

... (truncated)
module ME_MUX4B (a, b, d0, d1, d2, d3, z);
   input a, b, d0, d1, d2, d3 ;
   output z ;
   // note A is least significant select line.
   //  A B   Selected
   //  00     d0
   //  10     d1
   //  01     d2
   //  11     d3

   AMUX4A m0 (.S0(a), .S1(b), .I1(d0), .I2(d1), .I3(d2), .I4(d3), .O(z) );
endmodule


module ME_MUX4B_B (a, b, d0, d1, d2, d3, z);
   input a, b, d0, d1, d2, d3 ;
   output z ;
   // note A is least significant select line.
   //  A B   Selected
   //  00     d0
   //  10     d1
   //  01     d2
   //  11     d3
   AMUX4A m0 (.S0(a), .S1(b), .I1(d0), .I2(d1), .I3(d2), .I4(d3), .O(z) );
endmodule

module ME_NMUX5B (A, B, C, D0, D1, D2, D3, D4, notXout);
   input A, B, C, D0, D1, D2, D3, D4 ;
   output notXout ;
   // note A is least significant select line.
   //  A B C  Selected
   //  000    d0
   //  100    d1
   //  010    d2
   //  110    d3
   //  ??1    d4

   ME_MUX4B   m2 (A, B, D0, D1, D2, D3, T0);
   ME_NMUX2B  m1 (C, T0, D4, notXout) ;
endmodule


module ME_MUX8B (a, b, c, d0, d1, d2, d3, d4, d5, d6, d7, f);
   input a, b, c, d0, d1, d2, d3, d4, d5, d6, d7 ;
   output f ;
   // note A is least significant select line.

   ME_MUX4B m0 (a, b, d0, d1, d2, d3, z0);
   ME_MUX4B m1 (a, b, d4, d5, d6, d7, z1);
   ME_MUX2B m2 (c, z0, z1, f);
endmodule


module ME_MUX8B_B (a, b, c, d0, d1, d2, d3, d4, d5, d6, d7, f);
   input a, b, c, d0, d1, d2, d3, d4, d5, d6, d7 ;
   output f ;
   // note A is least significant select line.
   ME_MUX4B_B m0 (a, b, d0, d1, d2, d3, z0);
   ME_MUX4B_B m1 (a, b, d4, d5, d6, d7, z1);
   ME_MUX2B_B m2 (c, z0, z1, f);
endmodule


... (truncated)
module ME_MUX_2Bbit  ( notA, A, D0, D1, Xout ) ;
   input notA, A;
   input D0, D1;
   output Xout;
   JDB22A g0 ( .A1(notA), .A2(D0), .B1(A), .B2(D1), .O(Xout) );
endmodule



module ME_MUX_2B_Bbit  ( notA, A, D0, D1, Xout ) ;
   input notA, A;
   input D0, D1;
   output Xout;
   JDB22A g0 ( .A1(notA), .A2(D0), .B1(A), .B2(D1), .O(Xout) );
endmodule



module ME_NMUX_2Bbit  ( notA, A, D0, D1, Xout ) ;
   input notA, A;
   input D0, D1;
   output Xout;
   ME_NMUX2BA_B g0 ( .nota(notA), .a(A), .d0(D0), .d1(D1), .notX(Xout) );
endmodule



module ME_MUX_2B_Bbyte ( notA, A, D0, D1, Xout ) ;
   input notA, A;
   input  [7:0] D0, D1;
   output [7:0] Xout;
   ME_MUX_2B_Bbit g10 ( notA, A, D0[0], D1[0], Xout[0] );
   ME_MUX_2B_Bbit g11 ( notA, A, D0[1], D1[1], Xout[1] );
   ME_MUX_2B_Bbit g12 ( notA, A, D0[2], D1[2], Xout[2] );
   ME_MUX_2B_Bbit g13 ( notA, A, D0[3], D1[3], Xout[3] );
   ME_MUX_2B_Bbit g14 ( notA, A, D0[4], D1[4], Xout[4] );
   ME_MUX_2B_Bbit g15 ( notA, A, D0[5], D1[5], Xout[5] );
   ME_MUX_2B_Bbit g16 ( notA, A, D0[6], D1[6], Xout[6] );
   ME_MUX_2B_Bbit g17 ( notA, A, D0[7], D1[7], Xout[7] );
endmodule
 

... (truncated)
module ME_MUX_2Bbyte ( notA, A, D0, D1, Xout ) ;
   input notA, A;
   input  [7:0] D0, D1;
   output [7:0] Xout;
   ME_MUX_2Bbit g10 ( notA, A, D0[0], D1[0], Xout[0] );
   ME_MUX_2Bbit g11 ( notA, A, D0[1], D1[1], Xout[1] );
   ME_MUX_2Bbit g12 ( notA, A, D0[2], D1[2], Xout[2] );
   ME_MUX_2Bbit g13 ( notA, A, D0[3], D1[3], Xout[3] );
   ME_MUX_2Bbit g14 ( notA, A, D0[4], D1[4], Xout[4] );
   ME_MUX_2Bbit g15 ( notA, A, D0[5], D1[5], Xout[5] );
   ME_MUX_2Bbit g16 ( notA, A, D0[6], D1[6], Xout[6] );
   ME_MUX_2Bbit g17 ( notA, A, D0[7], D1[7], Xout[7] );
endmodule



module ME_NMUX_2Bbyte ( notA, A, D0, D1, Xout ) ;
   input notA, A;
   input  [7:0] D0, D1;
   output [7:0] Xout;
   ME_NMUX_2Bbit g10 ( notA, A, D0[0], D1[0], Xout[0] );