/******************************************************************************/
/* */
/* Copyright (c) 1999 Sun Microsystems, Inc. All rights reserved. */
/* */
/* The contents of this file are subject to the current version of the Sun */
/* Community Source License, microSPARCII ("the License"). You may not use */
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/* */
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/* */
/******************************************************************************/
// @(#)fdp.v 1.1 4/7/92
//
module fp_frac
(ss_clock,
FracAregLoadEn, FracAregLC,
FracBregLoadEn, FracBregLC,
FracCregLoadEn, FracCregLC,
FracTregLoadEn,
FracYbusLSBs,
InFromCregOr0, InForCreg, InForCregDB,
Constantb, Constantd, Constante, Constantf, Constantg, Constanth,
RS2_frac, RS1_frac,
SNnotDB, OprSNnotDB,
SRControl, SROneMore, SRToSticky,
SLControl,
LIB,
TopBitsIn,
notStickyInForSR, // For right
Shift, Pos, Zero, InitialMulStep,
/* notInitialSumZero, */
InitialCarryBit,
SumCarryLoadEn,
MulLenSel,
SumOut0, CarryOut0, CarryOut3,
LeftnotRight, FracALUOpSub, FracALUOpDiv,
notFracYFromD1, notFracYFromD2, notFracYFromD3,
/* notFracYFromD1A, notFracYFromD2A, notFracYFromD3A, */ //Copies
FracXFromB,
//ctl outputs
notSticky4, Sticky2, notSticky1, StickyExtra,
Creg_30_29, // CregSNBits = Creg[30:29]
Creg_56_55, // CregInSL2SQRT = Creg[56:55]
BregMaster_57, // FracBregSign
BregMaster_54, // BregFPMSBM1
notMultip,
notAM31_3, notAM2_0, // Inexact parts
StickyForSR1,
AregMaster_57_40, // AregMaster[57:40]
AregMaster_32, // AregMaster[32]
AregMaster_7_0, // AregMaster[7:0]
/* duplicate port--AregMasterFPMSBP1, */ // AregMasterBuf[56]
notAregMasterFPMSBP1,
Treg_1_0, // TregLSBs
SumInLSBs, CarryInLSBs,
SALSBs, SBLSBs, SCLSBs, // LSBs for cs array
CALSB , CBLSB , CCLSB ,
notFracZero, FracZero,
FracResult_57, // FracSign
SubResultNorm,
FracResult_56, // FracOverflow
FracResult_55_52, // StepRemBits
notPossibleOv,
FracResultBufout, // only bits [54:3] are used in result
ss_scan_mode, fp_frac_scan_in, fp_frac_scan_out);
input ss_clock
;
input FracAregLoadEn
;
input [2:0] FracAregLC
;
input FracBregLoadEn
;
input [2:0] FracBregLC
;
input [1:0] FracYbusLSBs
;
input FracCregLoadEn
, FracCregLC
,
FracTregLoadEn
;
input [54:0] RS2_frac
, RS1_frac
;
input SNnotDB
, OprSNnotDB
;
input Constantb
, Constantd
, Constante
, Constantf
, Constantg
, Constanth
;
input [1:0] InFromCregOr0
;
input [1:0] InForCreg
,
InForCregDB
;
input [3:0] SRControl
, SLControl
;
input [2:0] LIB
;
input SROneMore
, SRToSticky
;
input [8:0] TopBitsIn
;
input notStickyInForSR
;
input [3:0] Shift
, Pos
, Zero
;
input InitialMulStep
,
/* notInitialSumZero, */
InitialCarryBit
,
SumCarryLoadEn
;
input LeftnotRight
, FracALUOpSub
, FracALUOpDiv
;
input [4:0] MulLenSel
;
input SumOut0
, CarryOut0
, CarryOut3
;
input notFracYFromD1
, notFracYFromD2
, notFracYFromD3
,
/* input notFracYFromD1A, notFracYFromD2A, notFracYFromD3A, */
FracXFromB
;
input ss_scan_mode
, fp_frac_scan_in
;
output [3:0] notSticky4
;
output [1:0] Sticky2
;
output notSticky1
;
output [1:0] StickyExtra
;
output [8:0] notMultip
;
output [1:0] Treg_1_0
;
output [1:0] Creg_30_29
;
output [1:0] Creg_56_55
;
output StickyForSR1
;
output [17:0] AregMaster_57_40
;
output AregMaster_32
;
output [ 7:0] AregMaster_7_0
;
output notAM31_3
, notAM2_0
;
output BregMaster_54
;
output BregMaster_57
;
output notFracZero
, FracZero
;
output [3:0] FracResult_55_52
;
output FracResult_57
, FracResult_56
;
output notAregMasterFPMSBP1
;
output SubResultNorm
;
output [54:3] FracResultBufout
;
output [2:0] SumInLSBs
,
CarryInLSBs
;
output [1:0] SALSBs
, SBLSBs
, SCLSBs
;
output CALSB
, CBLSB
, CCLSB
;
output notPossibleOv
;
output fp_frac_scan_out
;
ME_TIEOFF toff (vdd
, gnd
);
// commented this out --
//assign fp_frac_scan_out = 1'bx ;
wire AregMasterFPMSBP1
;
wire [57:0] AregMaster
, AregMasterBuf
;
assign AregMaster_57_40 = AregMaster[57:40] ;
assign AregMaster_32 = AregMaster[32] ;
assign AregMaster_7_0 = AregMaster[7:0] ;
wire [57:0] BregMaster
;
assign BregMaster_54 = BregMaster[54] ;
assign BregMaster_57 = BregMaster[57] ;
wire [57:0] Creg
;
assign Creg_30_29 = Creg[30:29] ;
assign Creg_56_55 = Creg[56:55] ;
wire [57:0] FracResult
;
assign FracResult_55_52 = FracResult[55:52] ;
assign FracResult_57 = FracResult[57] ;
assign FracResult_56 = FracResult[56] ;
wire [57:0] FracResultBuf
;
assign FracResultBufout = FracResultBuf[54:3] ;
wire [57:0] Treg
;
assign Treg_1_0 = Treg[1:0];
// internal bus on fractions datapath
wire [57:1] SRResult
;
wire [57:0] SLResult
;
wire [57:0] SResult
, BregMasterBuf
, FracXbus
;
wire [57:2] FracYbus
;
wire [57-1:1] SD
;
wire [57-1:2] CD
;
// extended internal format operands
wire [57:0] OprA
, OprB
;
wire [51:0] FracOpA
, FracOpB
;
// note order of items is suggested order of functional units on datapath.
// Operand select (single/double) muxes
ME_MUX_2B_52 opifaxf (OprSNnotDB,
RS2_frac[51:0],
{RS2_frac[54:32],
gnd, gnd, gnd, gnd, gnd, gnd, gnd,
gnd, gnd, gnd, gnd, gnd, gnd, gnd,
gnd, gnd, gnd, gnd, gnd, gnd, gnd,
gnd, gnd, gnd, gnd, gnd, gnd, gnd,
gnd},
FracOpA[51:0]);
assign OprA = {gnd, gnd, vdd, FracOpA, gnd, gnd, gnd};
ME_MUX_2B_52 opifbxf (OprSNnotDB,
RS1_frac[51:0],
{RS1_frac[54:32],
gnd, gnd, gnd, gnd, gnd, gnd, gnd,
gnd, gnd, gnd, gnd, gnd, gnd, gnd,
gnd, gnd, gnd, gnd, gnd, gnd, gnd,
gnd, gnd, gnd, gnd, gnd, gnd, gnd,
gnd},
FracOpB[51:0]);
assign OprB = {gnd, gnd, vdd, FracOpB, gnd, gnd, gnd};
// Breg Input stuff
ME_FREGA_5_58 B (ss_clock,
FracBregLoadEn,
FracBregLC[0], FracBregLC[1], FracBregLC[2],
OprB, AregMasterBuf,
FracResultBuf,
{FracResultBuf[57-2:0], InFromCregOr0}, // FracResultSL2
{CD[57-1:2], CarryOut3, CarryOut0, gnd}, // MulResCarry For Breg
BregMaster,
BregMasterBuf,
notBregMSB
);
MultiplierSlice mu (ss_clock,
InitialMulStep,
/* dhn--01/10/91 notInitialSumZero, */
InitialCarryBit,
SumCarryLoadEn,
Shift, Pos, Zero,
SumOut0, CarryOut0, CarryOut3,
BregMasterBuf[57:1], SumInLSBs, CarryInLSBs,
SALSBs, SBLSBs, SCLSBs,
CALSB, CBLSB, CCLSB,
SD[57-1:1],
CD[57-1:2]);
ME_FREGA_2_58 C (ss_clock,
FracCregLoadEn, FracCregLC,
FracResultBuf,
{Creg[57-2:31],InForCreg, Creg[28:1], InForCregDB, gnd}, // CregSL2SQTDIV
Creg);
// ******** AREG *********************************
ME_INVA ifs (FracResult_57, notFracSign
); // used to be in divlog
ME_FREGA_8_58 A (ss_clock,
FracAregLoadEn,
FracAregLC[0], FracAregLC[1], FracAregLC[2],
OprA,
Creg,
BregMasterBuf, // 2 Allow speedy swapping
SResult, // 3
FracResultBuf,
{FracResultBuf[56:0], gnd}, // FracResultSL1
{AregMasterBuf[56:2], notFracSign, gnd, gnd},
{SD[57-1:1], CarryOut0, SumOut0}, // MulResSum ForAreg
AregMaster,
AregMasterBuf,
AregMasterFPMSBP1,
notAregMasterFPMSBP1);
// logic on output of areg in datapath
AregInexactSlice ax (AregMasterBuf[31:0], notAM31_3, notAM2_0);
MulSelSlice snmultip ( MulLenSel, AregMaster[8:0], AregMaster[40:32], notMultip );
// *************** end of Areg ************************************ //
// Shifter logic
ShiftRight shr (AregMasterBuf, SRControl, SROneMore,
SRToSticky, TopBitsIn,
notSticky4, Sticky2, notSticky1, StickyExtra,
SRResult[57:1]);
ShiftLeft shl (AregMasterBuf, SLControl, LIB,
SLResult);
ME_NMUX_2B_58 Smux (LeftnotRight, {SRResult[57:1], notStickyInForSR}, SLResult,
SResult);
ME_FREGA_1_58 T (ss_clock, FracTregLoadEn, FracResultBuf, Treg);
// *************** end of Treg ************************************ //
/*ME_MUX_4B_56 Ymux (notFracYFromD0,
notFracYFromD1,
{gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd,
gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd,
gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd,
gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd}, // 56'h0
{AregMasterBuf[57], AregMasterBuf[57:3]}, // AregMasterSR1[57:2]
AregMasterBuf[57:2],
Treg[57:2],
FracYbus[57:2]);*/
ME_YmuxSlice Ymux (notFracYFromD1, notFracYFromD2, notFracYFromD3,
/* dhn--01/10/91 notFracYFromD1A, notFracYFromD2A, notFracYFromD3A, */
{AregMasterBuf[57], AregMasterBuf[57:3]}, // AregMasterSR1[57:2]
AregMasterBuf[57:2],
Treg[57:2],
FracYbus[57:2]);
// send bottom two bits of Y to control logic
// assign FracYbusBSLSBs = FracYbus[1:0]; // ignored taken from AregMaster[2:0] and Treg[1:0]
// insert two bits from control logic into the low end of Ybus here
// *************** end of Ymux ************************************ //
ME_MUX_2B_B_58 Xbus (FracXFromB,
{ gnd, gnd, Constantb,
gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd,
gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd,
gnd, gnd, gnd, gnd, gnd, gnd, gnd,
Constantd,
Constante, Constante, Constante, Constante,
Constante, Constante, Constante, Constante,
Constante, Constante, Constante, Constante,
Constante, Constante, Constante, Constante,
Constante, Constante, Constante, Constante,
Constante, Constante, Constante, Constante,
Constante, Constante, Constante, Constante,
Constantf,
Constantg, Constantg}, // FracXConstant
BregMasterBuf, FracXbus);
AregLSBLog alsb (AregMaster[1:0], // AregLSBs[1:0]
AregMaster[33:32], // AregLSBSN
AregMaster[4:3], // AregLSBDB
AregMaster[56], // AregFPMSBP1
SNnotDB,
TrueIEEEAregLSB
,
StickyForSR1);
wire Eqv
;
AdderLSBlog fals (FracALUOpSub,
FracALUOpDiv,
notBregMSB, // notFracBregSign
Eqv,
Constanth, // notFracRNearest
TrueIEEEAregLSB,
Sub
, AdderCarryIn
,
notFracZero, FracZero);
ME_ADD_58 adr (Sub, AdderCarryIn,
FracXbus,
{FracYbus, FracYbusLSBs},
FracResult, FracResultBuf, Eqv);
/* ***************************** */
/* Deal with special result bits */
/* ***************************** */
CheckOverflow ov (FracResult[55+1:55-8], notPossibleOv, SubResultNorm);
endmodule
This page: |
Created: | Thu Aug 19 11:57:19 1999 |
| From: |
../../../sparc_v8/ssparc/fpu/fp_frac/rtl/fdp.v
|