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/******************************************************************************/ 
/*                                                                            */ 
/* Copyright (c) 1999 Sun Microsystems, Inc. All rights reserved.             */ 
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/******************************************************************************/ 
//  @(#)casegeneration.v	1.1  4/7/92
//
[Up: Control cg]
module CaseGeneration (
   Rom_Feedback,
   Rom_Condition,
   SubResultNorm,
   Cond_SignsDiffer,
   notExpUnderflow, notExpOverflow, notExpException, notPossibleOv, notFracZero,
   RCondition,
   Feedback);

input [4:0]Rom_Feedback;
input [3:0]Rom_Condition;
input SubResultNorm;
input Cond_SignsDiffer;
input notExpUnderflow, notExpOverflow, notExpException, notPossibleOv, notFracZero;
output [4:0]Feedback;
output RCondition;           // Speed critical signal


// ***************************************//
// Case Generation                        //
// ***************************************//


ME_INV_A cnsb (Rom_Condition[0], notCondSel0);
ME_AND3 cqsb  (Rom_Condition[1], Rom_Condition[2], Rom_Condition[3],
               Rom_Case);
ME_AND2 ril (Rom_Case, notCondSel0, Rom_Sub_Sign_Case);
ME_AND2_B ris (Rom_Case, Rom_Condition[0], RomRoundCase);

// ***************************************//
// Rounding Case Address Generation       //
// ***************************************//

wire [4:0] notUFeedback;


//ME_INVA  g1_0 (ExpUnderflow, notExpUnderflow);
//ME_INVA  g1_1 (ExpOverflow,  notExpOverflow);
//ME_AND2  fzfz (notExpUnderflow, notExpOverflow, notExpException);
// Note SubResultNorm and notPossibleOv are time critical

ME_NAND3_B nrc (SubResultNorm, notExpException, notPossibleOv,
            RCondition);
//ME_NAND4 nrc (SubResultNorm, notExpUnderflow, notExpOverflow, notPossibleOv,
//            RCondition);
//
// notRCondition(e)
// Ye Olde Criticale Pathe
//

// ***************************************//
// Sign Case Bits                         //
// ***************************************//


ME_NMUX2B vbxb (Rom_Sub_Sign_Case,
            Rom_Feedback[1],
            Cond_SignsDiffer,
            notUFeedback[1]);

// *********************************************************//
// Generate Feedback address including CASE logic           //
// *********************************************************//

ME_INV_A g0_0 (Rom_Feedback[0],   notUFeedback[0]);
ME_INV_A g0_2 (Rom_Feedback[2], notUFeedback[2]);
ME_INV_A g0_3 (Rom_Feedback[3], notUFeedback[3]);
ME_INV_A g0_4 (Rom_Feedback[4], notUFeedback[4]);

// Assign rounding case bits

ME_NMUX2B_B ufb0 (RomRoundCase, notUFeedback[0], notExpOverflow,  Feedback[0]);
ME_NMUX2B_B ufb1 (RomRoundCase, notUFeedback[1], notExpUnderflow, Feedback[1]);
ME_NMUX2B_B ufb2 (RomRoundCase, notUFeedback[2], SubResultNorm,   Feedback[2]);
ME_NMUX2B_B ufb3 (RomRoundCase, notUFeedback[3], notFracZero,     Feedback[3]);
ME_NMUX2B_B ufb4 (RomRoundCase, notUFeedback[4], notPossibleOv,   Feedback[4]);

endmodule

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This page: Created:Thu Aug 19 12:01:44 1999
From: ../../../sparc_v8/ssparc/fpu/fp_ctl/rtl/casegeneration.v

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