/******************************************************************************/ 
/*                                                                            */ 
/* Copyright (c) 1999 Sun Microsystems, Inc. All rights reserved.             */ 
/*                                                                            */ 
/* The contents of this file are subject to the current version of the Sun    */ 
/* Community Source License, microSPARCII ("the License"). You may not use    */ 
/* this file except in compliance with the License.  You may obtain a copy    */ 
/* of the License by searching for "Sun Community Source License" on the      */ 
/* World Wide Web at http://www.sun.com. See the License for the rights,      */ 
/* obligations, and limitations governing use of the contents of this file.   */ 
/*                                                                            */ 
/* Sun Microsystems, Inc. has intellectual property rights relating to the    */ 
/* technology embodied in these files. In particular, and without limitation, */ 
/* these intellectual property rights may include one or more U.S. patents,   */ 
/* foreign patents, or pending applications.                                  */ 
/*                                                                            */ 
/* Sun, Sun Microsystems, the Sun logo, all Sun-based trademarks and logos,   */ 
/* Solaris, Java and all Java-based trademarks and logos are trademarks or    */ 
/* registered trademarks of Sun Microsystems, Inc. in the United States and   */ 
/* other countries. microSPARC is a trademark or registered trademark of      */ 
/* SPARC International, Inc. All SPARC trademarks are used under license and  */ 
/* are trademarks or registered trademarks of SPARC International, Inc. in    */ 
/* the United States and other countries. Products bearing SPARC trademarks   */ 
/* are based upon an architecture developed by Sun Microsystems, Inc.         */ 
/*                                                                            */ 
/******************************************************************************/ 
`define dc_size1 (1 << 14 )

module dcache_ram  ( dout,din,ain,bw);
output [63:0] dout;
input  [63:0] din,bw;
input  [10:0] ain;

	// synopsys translate_off

	wire [10:0] dc_ain = ain ;
	wire [63:0] dc_di = din ;

	wire [0:7] we_  = ~({ 
		bw[56], bw[48], bw[40], bw[32], bw[24], bw[16], bw[8], bw[0]});

	wire [63:0] dc_do;
        assign dout[63:0] = dc_do[63:0];

	// ram instantiated
	reg [7:0] dc_ram [0:`dc_size1] ;  	// (2^14 - 1)

	// Read Dcache (Bypass is done outside).

	assign dc_do[63:56] = we_[0] ? dc_ram[{dc_ain,3'b000}] : 8'bx;
	assign dc_do[55:48] = we_[1] ? dc_ram[{dc_ain,3'b001}] : 8'bx;
	assign dc_do[47:40] = we_[2] ? dc_ram[{dc_ain,3'b010}] : 8'bx;
	assign dc_do[39:32] = we_[3] ? dc_ram[{dc_ain,3'b011}] : 8'bx;
	assign dc_do[31:24] = we_[4] ? dc_ram[{dc_ain,3'b100}] : 8'bx;
	assign dc_do[23:16] = we_[5] ? dc_ram[{dc_ain,3'b101}] : 8'bx;
	assign dc_do[15:8]  = we_[6] ? dc_ram[{dc_ain,3'b110}] : 8'bx;
	assign dc_do[7:0]   = we_[7] ? dc_ram[{dc_ain,3'b111}] : 8'bx;

	// Write Dcache

	always @(negedge we_[0]) dc_ram[{dc_ain,3'b000}] = dc_di[63:56] ;
	always @(negedge we_[1]) dc_ram[{dc_ain,3'b001}] = dc_di[55:48] ;
	always @(negedge we_[2]) dc_ram[{dc_ain,3'b010}] = dc_di[47:40] ;
	always @(negedge we_[3]) dc_ram[{dc_ain,3'b011}] = dc_di[39:32] ;
	always @(negedge we_[4]) dc_ram[{dc_ain,3'b100}] = dc_di[31:24] ;
	always @(negedge we_[5]) dc_ram[{dc_ain,3'b101}] = dc_di[23:16] ;
	always @(negedge we_[6]) dc_ram[{dc_ain,3'b110}] = dc_di[15:8]  ;
	always @(negedge we_[7]) dc_ram[{dc_ain,3'b111}] = dc_di[7:0]   ;

	// synopsys translate_on


endmodule