/******************************************************************************/ 
/*                                                                            */ 
/* Copyright (c) 1999 Sun Microsystems, Inc. All rights reserved.             */ 
/*                                                                            */ 
/* The contents of this file are subject to the current version of the Sun    */ 
/* Community Source License, microSPARCII ("the License"). You may not use    */ 
/* this file except in compliance with the License.  You may obtain a copy    */ 
/* of the License by searching for "Sun Community Source License" on the      */ 
/* World Wide Web at http://www.sun.com. See the License for the rights,      */ 
/* obligations, and limitations governing use of the contents of this file.   */ 
/*                                                                            */ 
/* Sun Microsystems, Inc. has intellectual property rights relating to the    */ 
/* technology embodied in these files. In particular, and without limitation, */ 
/* these intellectual property rights may include one or more U.S. patents,   */ 
/* foreign patents, or pending applications.                                  */ 
/*                                                                            */ 
/* Sun, Sun Microsystems, the Sun logo, all Sun-based trademarks and logos,   */ 
/* Solaris, Java and all Java-based trademarks and logos are trademarks or    */ 
/* registered trademarks of Sun Microsystems, Inc. in the United States and   */ 
/* other countries. microSPARC is a trademark or registered trademark of      */ 
/* SPARC International, Inc. All SPARC trademarks are used under license and  */ 
/* are trademarks or registered trademarks of SPARC International, Inc. in    */ 
/* the United States and other countries. Products bearing SPARC trademarks   */ 
/* are based upon an architecture developed by Sun Microsystems, Inc.         */ 
/*                                                                            */ 
/******************************************************************************/ 
// @(#)mc_dcache.v	1.35 9/15/93
// This file contains the Dcache SRAM Megacell Model


module mc_dcache (
        dt_di,
        dt_val_in,
        dt_cntx_in,
        dt_be,
        dt_be_vb,
        dt_be_cb,
        dt_acc_in,
//	export_dc_scan_vec,
//	import_dt_scan_vec,
 	dc_hld,
	dc_do, 
	dc_ain,
	dc_di, 
	dc_wle, 
	dc_be, 
	dc_power_down,
	dt_power_down,
        dc_iiddtn,
	dt_wle, 
	dt_ain, 
	dc_scan_mode,
	dc_scan_in,
	dc_scan_out,
	dc_tg_strobe,
	dc_clk
	);

        input [31:13] dt_di;
        input dt_val_in;
        input [7:0] dt_cntx_in;
        input dt_be;
        input dt_be_vb;
        input dt_be_cb;
        input [4:0] dt_acc_in;

//	input [104:0] import_dt_scan_vec;
	input [1:0] dc_hld ; 	// Synchronous hold asserted when "1"
	input dc_power_down ; 	// Synchronous power down for D$
        input dc_iiddtn ;
	input [(`dc_msb-3):0] dc_ain ; 	// 2^10 cache lines 
	input [63:0] dc_di ;
	input [7:0] dc_be ;
	input dc_wle ;
	input dc_clk ;
	input dc_scan_mode ;
	input dc_scan_in ;
	input dc_tg_strobe ;

//	output [104:0] export_dc_scan_vec;
	output [`dc_msb:4] dt_ain ;
	output dt_wle ;
	output dt_power_down ; 	// Synchronous power down for DT
	output dc_scan_out ;
	output [63:0] dc_do ;


	wire logic_0 = 1'b0 ;  // To suppress errors from $toggle tools
	wire [(`dc_msb-3):0] adr, adr_in ;
	wire wle, wle_in ;
	wire [7:0] be, be_in ;
	wire [63:0] di, di_in ;
	wire power_down_w, power_down_w_in ;

	// Use this dummy bus to avoid port size mismatches but still
	//     allow addressing a 64KB cache in cache mode.
	wor [(17-`log2_dcachesize):1] ain_pad ; // [1:1] or [4:1]
	// Mflipflop_noop_14 ain_reg({ain_pad,adr}, {ain_pad,adr_in}, dc_clk) ;
	// Leave this out of scan. This is only for cache mode.
	Mflipflop_noop_4 ain_pad_reg(ain_pad, ain_pad, dc_clk) ;

	// 4 copies of this
	Mflipflop_noop_1 ain_reg(adr[0], adr_in[0], dc_clk) ;


	// 8 copies of this
	Mflipflop_noop_1 ain_reg_1(adr[1], adr_in[1], dc_clk) ;


	// 4 copies of this
	Mflipflop_noop_2 ain_reg_23(adr[3:2], adr_in[3:2], dc_clk) ;


	// 2 copies of this
	Mflipflop_noop_6 ain_reg_4_9(adr[(`dc_msb-3):4], adr_in[(`dc_msb-3):4], 
			dc_clk);


	// 4 copies of this (32 x 2) bit register
	Mflipflop_32 di_regh(di[63:32], di_in[63:32],
			dc_clk, dc_hld[0] ) ;
	Mflipflop_32 di_regl(di[31:0], di_in[31:0],
			dc_clk, dc_hld[1] ) ;


	// 2 copies
	Mflipflop_noop dc_wle_reg (wle, wle_in, dc_clk) ;


	// 4 copies
	Mflipflop_noop_8 dc_be_reg (be[7:0], be_in[7:0], dc_clk) ;


	// 6 copies
	Mflipflop_noop pd_reg (power_down_w, power_down_in, dc_clk);


        // 4 unused f/f's in the D$/DT scan chain. This was done so that it 
        // would be easy to layout some(?) registers without breaking symmetry.

        // Scan out connected only when CACHESCAN is enabled.
	wire dc_scan_out;

	assign dt_power_down = power_down_w;
	assign dt_wle = wle;
	// Send all address bits except the lsb, since the tags dont need it.
	assign dt_ain[`dc_msb:4] = adr[(`dc_msb-3):1];

	////////////////////////////////////////////////////////////////

	wire unknown_output = (power_down_w !=1'b0);

	// Dcache Bypass cycle
	wire [63:0] dc_do, dc_do_int;

        assign dc_do[63:56] =
		unknown_output 
				? 8'bx : (
            		be[0] ? di[63:56] : dc_do_int[63:56] ) ;
        assign dc_do[55:48] =
		unknown_output 
				? 8'bx : (
            		be[1] ? di[55:48] : dc_do_int[55:48] ) ;
        assign dc_do[47:40] =
		unknown_output 
				? 8'bx : (
            		be[2] ? di[47:40] : dc_do_int[47:40] ) ;
        assign dc_do[39:32] =
		unknown_output 
				? 8'bx : (
            		be[3] ? di[39:32] : dc_do_int[39:32] ) ;
        assign dc_do[31:24] =
		unknown_output 
				? 8'bx : (
            		be[4] ? di[31:24] : dc_do_int[31:24] ) ;
        assign dc_do[23:16] =
		unknown_output 
				? 8'bx : (
            		be[5] ? di[23:16] : dc_do_int[23:16] ) ;
        assign dc_do[15:8] =
		unknown_output 
				? 8'bx : (
            		be[6] ? di[15:8] : dc_do_int[15:8] ) ;
        assign dc_do[7:0] =
		unknown_output 
				? 8'bx : (
            		be[7] ? di[7:0] : dc_do_int[7:0] ) ;

	// Dcache Read/Write cycle
        wire we_ctrl      =   wle & ~dc_scan_mode & ~power_down_w ;
        wire [7:0] we     =   {8{we_ctrl}} & be[7:0] ;
        wire [63:0] di_int =  
					di ; 
	wire dram_clk = dc_clk & dc_tg_strobe;

	assign 
	{ adr_in, wle_in, be_in, power_down_in, di_in } =
	{ dc_ain, dc_wle, dc_be, dc_power_down, dc_di};

	wire one = 1'b1;
	wire [7:0] wep = ~(~{we[7:0] & {8{~dram_clk}}});

// Turn off dram on power down and IDDQ test 

// fix for rel 1.0 

	wire dc_iiddtn_ = ~dc_iiddtn;

//        wire shutoff_dram = power_down_w | dc_iiddtn ;
        wire shutoff_dram = ~(power_down_w | dc_iiddtn_) ;
/*
	RR1024X64	dram	(
	.DO63(dc_do_int[63]),
	.DO62(dc_do_int[62]),
	.DO61(dc_do_int[61]),
	.DO60(dc_do_int[60]),
	.DO59(dc_do_int[59]),
	.DO58(dc_do_int[58]),
	.DO57(dc_do_int[57]),
	.DO56(dc_do_int[56]),
	.DO55(dc_do_int[55]),
	.DO54(dc_do_int[54]),
	.DO53(dc_do_int[53]),
	.DO52(dc_do_int[52]),
	.DO51(dc_do_int[51]),
	.DO50(dc_do_int[50]),
	.DO49(dc_do_int[49]),
	.DO48(dc_do_int[48]),
	.DO47(dc_do_int[47]),
	.DO46(dc_do_int[46]),
	.DO45(dc_do_int[45]),
	.DO44(dc_do_int[44]),
	.DO43(dc_do_int[43]),
	.DO42(dc_do_int[42]),
	.DO41(dc_do_int[41]),
	.DO40(dc_do_int[40]),
	.DO39(dc_do_int[39]),
	.DO38(dc_do_int[38]),
	.DO37(dc_do_int[37]),
	.DO36(dc_do_int[36]),
	.DO35(dc_do_int[35]),
	.DO34(dc_do_int[34]),
	.DO33(dc_do_int[33]),
	.DO32(dc_do_int[32]),
	.DO31(dc_do_int[31]),
	.DO30(dc_do_int[30]),
	.DO29(dc_do_int[29]),
	.DO28(dc_do_int[28]),
	.DO27(dc_do_int[27]),
	.DO26(dc_do_int[26]),
	.DO25(dc_do_int[25]),
	.DO24(dc_do_int[24]),
	.DO23(dc_do_int[23]),
	.DO22(dc_do_int[22]),
	.DO21(dc_do_int[21]),
	.DO20(dc_do_int[20]),
	.DO19(dc_do_int[19]),
	.DO18(dc_do_int[18]),
	.DO17(dc_do_int[17]),
	.DO16(dc_do_int[16]),
	.DO15(dc_do_int[15]),
	.DO14(dc_do_int[14]),
	.DO13(dc_do_int[13]),
	.DO12(dc_do_int[12]),
	.DO11(dc_do_int[11]),
	.DO10(dc_do_int[10]),
	.DO9(dc_do_int[09]),
	.DO8(dc_do_int[08]),
	.DO7(dc_do_int[07]),
	.DO6(dc_do_int[06]),
	.DO5(dc_do_int[05]),
	.DO4(dc_do_int[04]),
	.DO3(dc_do_int[03]),
	.DO2(dc_do_int[02]),
	.DO1(dc_do_int[01]),
	.DO0(dc_do_int[00]),
	.WE63(wep[0]),
	.WE62(wep[0]),
	.WE61(wep[0]),
	.WE60(wep[0]),
	.WE59(wep[0]),
	.WE58(wep[0]),
	.WE57(wep[0]),
	.WE56(wep[0]),
	.WE55(wep[1]),
	.WE54(wep[1]),
	.WE53(wep[1]),
	.WE52(wep[1]),
	.WE51(wep[1]),
	.WE50(wep[1]),
	.WE49(wep[1]),
	.WE48(wep[1]),
	.WE47(wep[2]),
	.WE46(wep[2]),
	.WE45(wep[2]),
	.WE44(wep[2]),
	.WE43(wep[2]),
	.WE42(wep[2]),
	.WE41(wep[2]),
	.WE40(wep[2]),
	.WE39(wep[3]),
	.WE38(wep[3]),
	.WE37(wep[3]),
	.WE36(wep[3]),
	.WE35(wep[3]),
	.WE34(wep[3]),
	.WE33(wep[3]),
	.WE32(wep[3]),
	.WE31(wep[4]),
	.WE30(wep[4]),
	.WE29(wep[4]),
	.WE28(wep[4]),
	.WE27(wep[4]),
	.WE26(wep[4]),
	.WE25(wep[4]),
	.WE24(wep[4]),
	.WE23(wep[5]),
	.WE22(wep[5]),
	.WE21(wep[5]),
	.WE20(wep[5]),
	.WE19(wep[5]),
	.WE18(wep[5]),
	.WE17(wep[5]),
	.WE16(wep[5]),
	.WE15(wep[6]),
	.WE14(wep[6]),
	.WE13(wep[6]),
	.WE12(wep[6]),
	.WE11(wep[6]),
	.WE10(wep[6]),
	.WE9(wep[6]),
	.WE8(wep[6]),
	.WE7(wep[7]),
	.WE6(wep[7]),
	.WE5(wep[7]),
	.WE4(wep[7]),
	.WE3(wep[7]),
	.WE2(wep[7]),
	.WE1(wep[7]),
	.WE0(wep[7]),
	//.CS(one),
        .CS(shutoff_dram),
	.OE63(one),
	.OE62(one),
	.OE61(one),
	.OE60(one),
	.OE59(one),
	.OE58(one),
	.OE57(one),
	.OE56(one),
	.OE55(one),
	.OE54(one),
	.OE53(one),
	.OE52(one),
	.OE51(one),
	.OE50(one),
	.OE49(one),
	.OE48(one),
	.OE47(one),
	.OE46(one),
	.OE45(one),
	.OE44(one),
	.OE43(one),
	.OE42(one),
	.OE41(one),
	.OE40(one),
	.OE39(one),
	.OE38(one),
	.OE37(one),
	.OE36(one),
	.OE35(one),
	.OE34(one),
	.OE33(one),
	.OE32(one),
	.OE31(one),
	.OE30(one),
	.OE29(one),
	.OE28(one),
	.OE27(one),
	.OE26(one),
	.OE25(one),
	.OE24(one),
	.OE23(one),
	.OE22(one),
	.OE21(one),
	.OE20(one),
	.OE19(one),
	.OE18(one),
	.OE17(one),
	.OE16(one),
	.OE15(one),
	.OE14(one),
	.OE13(one),
	.OE12(one),
	.OE11(one),
	.OE10(one),
	.OE9(one),
	.OE8(one),
	.OE7(one),
	.OE6(one),
	.OE5(one),
	.OE4(one),
	.OE3(one),
	.OE2(one),
	.OE1(one),
	.OE0(one),
	.DI63(di_int[63]),
	.DI62(di_int[62]),
	.DI61(di_int[61]),
	.DI60(di_int[60]),
	.DI59(di_int[59]),
	.DI58(di_int[58]),
	.DI57(di_int[57]),
	.DI56(di_int[56]),
	.DI55(di_int[55]),
	.DI54(di_int[54]),
	.DI53(di_int[53]),
	.DI52(di_int[52]),
	.DI51(di_int[51]),
	.DI50(di_int[50]),
	.DI49(di_int[49]),
	.DI48(di_int[48]),
	.DI47(di_int[47]),
	.DI46(di_int[46]),
	.DI45(di_int[45]),
	.DI44(di_int[44]),
	.DI43(di_int[43]),
	.DI42(di_int[42]),
	.DI41(di_int[41]),
	.DI40(di_int[40]),
	.DI39(di_int[39]),
	.DI38(di_int[38]),
	.DI37(di_int[37]),
	.DI36(di_int[36]),
	.DI35(di_int[35]),
	.DI34(di_int[34]),
	.DI33(di_int[33]),
	.DI32(di_int[32]),
	.DI31(di_int[31]),
	.DI30(di_int[30]),
	.DI29(di_int[29]),
	.DI28(di_int[28]),
	.DI27(di_int[27]),
	.DI26(di_int[26]),
	.DI25(di_int[25]),
	.DI24(di_int[24]),
	.DI23(di_int[23]),
	.DI22(di_int[22]),
	.DI21(di_int[21]),
	.DI20(di_int[20]),
	.DI19(di_int[19]),
	.DI18(di_int[18]),
	.DI17(di_int[17]),
	.DI16(di_int[16]),
	.DI15(di_int[15]),
	.DI14(di_int[14]),
	.DI13(di_int[13]),
	.DI12(di_int[12]),
	.DI11(di_int[11]),
	.DI10(di_int[10]),
	.DI9(di_int[09]),
	.DI8(di_int[08]),
	.DI7(di_int[07]),
	.DI6(di_int[06]),
	.DI5(di_int[05]),
	.DI4(di_int[04]),
	.DI3(di_int[03]),
	.DI2(di_int[02]),
	.DI1(di_int[01]),
	.DI0(di_int[00]),
	.ADR9(adr[09]),
	.ADR8(adr[08]),
	.ADR7(adr[07]),
	.ADR6(adr[06]),
	.ADR5(adr[05]),
	.ADR4(adr[04]),
	.ADR3(adr[03]),
	.ADR2(adr[02]),
	.ADR1(adr[01]),
	.ADR0(adr[00]));

*/

dcache_ram dram ( .dout(dc_do_int[63:0]),
		  .din(di_int[63:0]),
		  .ain({1'b0,adr[9:0]}),
.bw({{8{wep[0]}},{8{wep[1]}},{8{wep[2]}},{8{wep[3]}},{8{wep[4]}},{8{wep[5]}},{8{wep[6]}},{8{wep[7]}}}
)
		);

endmodule