/******************************************************************************/
/* */
/* Copyright (c) 1999 Sun Microsystems, Inc. All rights reserved. */
/* */
/* The contents of this file are subject to the current version of the Sun */
/* Community Source License, microSPARCII ("the License"). You may not use */
/* this file except in compliance with the License. You may obtain a copy */
/* of the License by searching for "Sun Community Source License" on the */
/* World Wide Web at http://www.sun.com. See the License for the rights, */
/* obligations, and limitations governing use of the contents of this file. */
/* */
/* Sun Microsystems, Inc. has intellectual property rights relating to the */
/* technology embodied in these files. In particular, and without limitation, */
/* these intellectual property rights may include one or more U.S. patents, */
/* foreign patents, or pending applications. */
/* */
/* Sun, Sun Microsystems, the Sun logo, all Sun-based trademarks and logos, */
/* Solaris, Java and all Java-based trademarks and logos are trademarks or */
/* registered trademarks of Sun Microsystems, Inc. in the United States and */
/* other countries. microSPARC is a trademark or registered trademark of */
/* SPARC International, Inc. All SPARC trademarks are used under license and */
/* are trademarks or registered trademarks of SPARC International, Inc. in */
/* the United States and other countries. Products bearing SPARC trademarks */
/* are based upon an architecture developed by Sun Microsystems, Inc. */
/* */
/******************************************************************************/
// @(#)entrycheck.v 1.1 4/7/92
//
module EntryCheck
(notRomMIptr, EntryPoint, s_mov);
input [7:0] notRomMIptr
;
output EntryPoint
, s_mov
;
wire [7:0] RomMIptr
;
ME_INV_B i_0 (notRomMIptr[0], RomMIptr[0]);
ME_INV_B i_1 (notRomMIptr[1], RomMIptr[1]);
ME_INV_B i_2 (notRomMIptr[2], RomMIptr[2]);
ME_INV_B i_3 (notRomMIptr[3], RomMIptr[3]);
ME_INV_B i_4 (notRomMIptr[4], RomMIptr[4]);
ME_INV_B i_5 (notRomMIptr[5], RomMIptr[5]);
ME_INV_B i_6 (notRomMIptr[6], RomMIptr[6]);
ME_INV_B i_7 (notRomMIptr[7], RomMIptr[7]);
ME_NOR3 g_1 (RomMIptr[7], RomMIptr[1], RomMIptr[0], s_0
);
ME_NOR2 g_2 (RomMIptr[4], RomMIptr[3], s_1
);
ME_NAND2 g_3 (RomMIptr[6], RomMIptr[2], s_2
);
ME_NAND4 g_4 (RomMIptr[5], s_0, s_1, s_2, s_mov);
ME_XOR2 g_5 (RomMIptr[4], RomMIptr[5], s_3
);
ME_NAND3 g_6 (RomMIptr[3], s_0, s_3, s_dyadic
);
ME_NOR4 g_7 (RomMIptr[7], RomMIptr[3], RomMIptr[2], RomMIptr[1], s_4
);
ME_AND2 g_8 (RomMIptr[6], RomMIptr[0], s_5
);
ME_NAND3 g_9 (s_4, s_5, s_3, s_sqrt
);
ME_NOR3 g_0 (RomMIptr[7], RomMIptr[6], RomMIptr[0], s_6
);
ME_AND2 h_1 (RomMIptr[3], RomMIptr[1], s_7
);
ME_NAND3 h_2 (s_6, s_7, s_3, s_cmp
);
ME_NOR3 h_3 (RomMIptr[6], RomMIptr[5], RomMIptr[1], s_8
);
ME_NAND2 h_4 (s_8, RomMIptr[2], s_9
);
ME_NOR3 h_5 (RomMIptr[4], RomMIptr[2], RomMIptr[1], s_10
);
ME_NAND2 h_6 (s_10, RomMIptr[6], s_11
);
ME_NOR2 h_7 (RomMIptr[6], RomMIptr[2], s_12
);
ME_NAND3 h_8 (s_12, s_3, RomMIptr[1], s_13
);
ME_NAND3 h_9 (s_13, s_11, s_9, s_14
);
//ME_INVA h_0 (RomMIptr[0], s_15);
ME_NAND4 j_1 (notRomMIptr[0], s_14, RomMIptr[3], RomMIptr[7], s_conv
);
ME_AND4 j_2 (s_mov, s_dyadic, s_sqrt, s_cmp, s_16
);
ME_NAND2 j_3 (s_conv, s_16, EntryPoint);
endmodule
This page: |
Created: | Thu Aug 19 12:00:47 1999 |
| From: |
../../../sparc_v8/ssparc/fpu/fp_ctl/rtl/entrycheck.v
|