/******************************************************************************/
/* */
/* Copyright (c) 1999 Sun Microsystems, Inc. All rights reserved. */
/* */
/* The contents of this file are subject to the current version of the Sun */
/* Community Source License, microSPARCII ("the License"). You may not use */
/* this file except in compliance with the License. You may obtain a copy */
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/* */
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/* registered trademarks of Sun Microsystems, Inc. in the United States and */
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/******************************************************************************/
/***************************************************************************
****************************************************************************
***
*** Program File: @(#)fpusas_sig.v
***
****************************************************************************
****************************************************************************/
//**************************************************************
// Dummy simulation module (should NOT go into the final hardware)
//
// Generates the signals needed for MPSAS instruction-by-instruction
// compare.
//**************************************************************
module fpusas_sig
;
// "output" signals
wire fpu_trap
; // FP inst. which caused trap is in R-stage
wire clock
= Msystem.clock ; // system clock
wire reset
= `SS_SCOPE.reset ; // system reset
wire ext_hold
= `FPU.ext_hold ; // IU hold signal
wire ext_flush
= `FPU.fpfpc.ext_flush ;
wire fold_annul_e
= `FPU.fpfpc.fold_annul_e ;
wire ffclr
= ~(reset | (ext_flush & ~ext_hold)) ;
reg [3:0] defer_done_w
; // FPop finished in W-stage
reg [3:0] defer_done_r
; // FPop finished in R-stage when hold==1
reg [3:0] defer_done_val
; // FPop finished after issue to mpsas
reg [3:0] fpop_done
; // number of FPops to compare in this cycle
reg fpop_deferred
;
// IU pipeline simulation values
wire [31:2] pc_w
= Mtask.complete.w_pc[31:2] ;
wire [31:2] pc_r
= Mtask.complete.r_pc_almost[31:2] ;
wire [31:0] ir_w
= Mtask.complete.w_decode_inst[31:0] ;
wire [31:0] ir_r
= Mtask.complete.r_decode_inst[31:0] ;
// FPU fq0 values
wire [31:2] pc_fq0
= `FPU.fpfpc.fpqst.qa_0[31:2] ;
wire [31:0] ir_fq0
= {2'b10,
`FPU.fpfpc.fpqst.qi_0[24:20],
5'b11010,
`FPU.fpfpc.fpqst.qi_0[19:0] };
// pipelined queue not empty signal
wire qne_r
= `fp_fpc.fpc.qctl1.qne_r ;
// Result writeback signal
wire fpop_wb
= `FPU.fpfpc.fpc.qctl1.writeback_q0 ;
// load enable for fsr register
wire fsr_ld
= `FPU.fpfpc.fpc.statctl1.fsr_ld ;
// execute mode
wire exemode
= `FPU.fpfpc.fpc.statctl1.exemode ;
// pending exc mode next cycle
wire i_pendmode
= `FPU.fpfpc.fpc.statctl1.ipendmode ;
// ext_fexc next cycle
wire i_fexc
= `FPU.fpfpc.fpc.statctl1.i_fexc ;
// fpu trap deferred to keep from confusing
// the poor mmu/cache controllers
wire deferred_trap
= i_pendmode & ~i_fexc ;
// fpop generating an exception
wire fpop_pend
= fpop_wb & (exemode & i_pendmode) ;
// Floating pt. exception acknowledge
wire ext_fxack
= `FPU.ext_fxack & ~ext_hold ;
// pipeline of fpop_e signal
wire fpop_e
= `FPU.fpfpc.fpc.fhold1.fpop_e ;
ME_FDS2LP wfpop_ff(.q(fpop_w
), .cp(clock), .cr(ffclr), .ld(~ext_hold),
.d(fpop_e));
ME_FDS2LP rfpop_ff(.q(fpop_r
), .cp(clock), .cr(ffclr), .ld(~ext_hold),
.d(fpop_w));
// pipeline of fp branch instruction
wire [4:0] dir_op_op2
= {`FPU.fpfpc.fpc.ir_d[31:30],
`FPU.fpfpc.fpc.ir_d[24:22] } ;
wire fbcc_d
= (dir_op_op2 == 5'o06) ;
wire finst_nostore_d
= `FPU.fpfpc.fpc.fhold1.finst_nostore_d ;
wire fstore_d
= `FPU.fpfpc.fpc.fhold1.fstore_d ;
// fp instruction in D
wire finst_d
= finst_nostore_d | fstore_d | fbcc_d ;
ME_FDS2LP fpins_e_ff(.q(finst_e_nval
), .cp(clock), .cr(ffclr), .ld(~ext_hold),
.d(finst_d));
wire finst_e
= finst_e_nval & ~fold_annul_e ;
ME_FDS2LP fpins_w_ff(.q(finst_w
), .cp(clock), .cr(ffclr), .ld(~ext_hold),
.d(finst_e));
ME_FDS2LP fpins_r_ff(.q(finst_r
), .cp(clock), .cr(ffclr), .ld(~ext_hold),
.d(finst_w));
// pipeline of fload signals
wire fload_r
= `FPU.fpfpc.fpc.fhold1.fload_r ;
// The real FPU can finish FPops before they're
// even issued to mpsas, so this series of
// counters keeps track of things.
always @ (posedge clock) begin
#2 ; // delay must be > 1
if (!ext_hold) begin // update deferred regs
if ((defer_done_r > 0) && (defer_done_w == 0)) begin
fpop_done = fpop_done + defer_done_r ;
defer_done_r = 0 ;
end
else if (defer_done_r > 2) begin
fpop_done = fpop_done + 1 ;
defer_done_r = defer_done_r - 1 ;
end
if (defer_done_w > 0) begin
defer_done_r = defer_done_r + defer_done_w ;
defer_done_w = 0 ;
end
end
if (defer_done_val > 0) begin
fpop_done = fpop_done + defer_done_val ;
defer_done_val = 0 ;
end
if (fpop_wb) begin
if ((pc_w === pc_fq0) && (ir_w === ir_fq0)) begin
if (ext_hold === 1) begin
defer_done_w = defer_done_w + 1 ; // FPop held in W-stage
end
else begin
defer_done_r = defer_done_r + 1 ; // FPop moving W->R
end
end
else if (((pc_r === pc_fq0) && (ir_r === ir_fq0) && ext_hold) ||
(fload_r & ext_hold) || // delay cmp if ld in R
(fpop_pend & ((finst_w & ~ext_hold) | (finst_r & ext_hold)))
)
begin
if ( ~deferred_trap ) begin
defer_done_r = defer_done_r + 1 ; // FPop held in R-stage
end
else begin
defer_done_w = defer_done_w + 1 ; // wait for next stage
end
end
else begin
if ( ~deferred_trap ) begin
defer_done_val = defer_done_val + 1 ; // FPop passed R-stage
end
else begin
defer_done_w = defer_done_w + 1 ; // wait for next stage
end
end
end
// reasons to delay fld compare
fpop_deferred = (defer_done_w > 0) || (defer_done_r > 0) ||
(defer_done_val > 0) ;
end
// delay trap acknowledge by 1 cycle
ME_FD1P trap_ff (.q(fpu_trap), .cp(clock), .d(ext_fxack)) ;
initial begin
defer_done_w = 4'b0 ;
defer_done_r = 4'b0 ;
defer_done_val = 4'b0 ;
fpop_done = 4'b0 ;
fpop_deferred = 1'b0 ;
end
wire [31:0] fsr
= `fp_fpc.fpqst.fsr ;
// task to view the fsr in verilog
task disp_fsr ;
begin
$display("FSR: rd ** tem ns res ver ftt qne * fcc aexc cexc");
$display(" -- -- ----- -- --- --- --- --- - --- ----- -----");
$display("%x: %b %b %b %b %b %b %b %b %b %b %b %b",
fsr,
fsr[31:30],fsr[29:28],
fsr[27:23],fsr[22],fsr[21:20],
fsr[19:17],fsr[16:14],
fsr[13],fsr[12],
fsr[11:10],fsr[9:5],
fsr[4:0]);
$display("");
end
endtask // disp_fsr
endmodule
This page: |
Created: | Thu Aug 19 12:00:00 1999 |
| From: |
../../../sparc_v8/ssparc/fpu/rtl/fpusas_sig.v
|