/******************************************************************************/ 
/*                                                                            */ 
/* Copyright (c) 1999 Sun Microsystems, Inc. All rights reserved.             */ 
/*                                                                            */ 
/* The contents of this file are subject to the current version of the Sun    */ 
/* Community Source License, microSPARCII ("the License"). You may not use    */ 
/* this file except in compliance with the License.  You may obtain a copy    */ 
/* of the License by searching for "Sun Community Source License" on the      */ 
/* World Wide Web at http://www.sun.com. See the License for the rights,      */ 
/* obligations, and limitations governing use of the contents of this file.   */ 
/*                                                                            */ 
/* Sun Microsystems, Inc. has intellectual property rights relating to the    */ 
/* technology embodied in these files. In particular, and without limitation, */ 
/* these intellectual property rights may include one or more U.S. patents,   */ 
/* foreign patents, or pending applications.                                  */ 
/*                                                                            */ 
/* Sun, Sun Microsystems, the Sun logo, all Sun-based trademarks and logos,   */ 
/* Solaris, Java and all Java-based trademarks and logos are trademarks or    */ 
/* registered trademarks of Sun Microsystems, Inc. in the United States and   */ 
/* other countries. microSPARC is a trademark or registered trademark of      */ 
/* SPARC International, Inc. All SPARC trademarks are used under license and  */ 
/* are trademarks or registered trademarks of SPARC International, Inc. in    */ 
/* the United States and other countries. Products bearing SPARC trademarks   */ 
/* are based upon an architecture developed by Sun Microsystems, Inc.         */ 
/*                                                                            */ 
/******************************************************************************/ 

module icache_ram  ( dout,din,ain,bw);
output [63:0] dout;
input  [63:0] din,bw;
input  [10:0] ain;


	wire [(`ic_msb-3):0] ic_ain = ain;
	wire [63:0] ic_di = din;
//	Eagle Note:  RAM has 32 bit write-enables. Other
//		RAM has 1 bit write-enables.  Just pick off one
//		bit-wise write-enables for each 32 bits.
	wire [0:1] we_ = ~( {bw[63], bw[31]});

	wire [63:0] ic_do;

        assign dout = ic_do ;

	// synopsys translate_off

	// ram instantiated
	reg [7:0] ic_ram [0:`ic_size] ; 	// (2^14 - 1)

	// Read Icache, (bypass is done outside).

	assign ic_do[63:32] = 
		      we_[0] ? {ic_ram[{ic_ain,3'b000}],
                		ic_ram[{ic_ain,3'b001}],
                		ic_ram[{ic_ain,3'b010}],
                		ic_ram[{ic_ain,3'b011}]
				} 
				: 32'bx;

	assign ic_do[31:0] = 
		      we_[1] ? {ic_ram[{ic_ain,3'b100}],
                		ic_ram[{ic_ain,3'b101}],
                		ic_ram[{ic_ain,3'b110}],
                		ic_ram[{ic_ain,3'b111}]
        			} 
				: 32'bx;
	// Write Icache.

	always @(negedge we_[0]) begin
		ic_ram[{ic_ain,3'b000}] = ic_di[63:56] ;
		ic_ram[{ic_ain,3'b001}] = ic_di[55:48] ;
		ic_ram[{ic_ain,3'b010}] = ic_di[47:40] ;
		ic_ram[{ic_ain,3'b011}] = ic_di[39:32] ;
	end		

	always @(negedge we_[1]) begin
                ic_ram[{ic_ain,3'b100}] = ic_di[31:24] ;
                ic_ram[{ic_ain,3'b101}] = ic_di[23:16] ;
                ic_ram[{ic_ain,3'b110}] = ic_di[15:8]  ;
                ic_ram[{ic_ain,3'b111}] = ic_di[7:0]   ;
	end

	// synopsys translate_on
endmodule