/******************************************************************************/
/* */
/* Copyright (c) 1999 Sun Microsystems, Inc. All rights reserved. */
/* */
/* The contents of this file are subject to the current version of the Sun */
/* Community Source License, microSPARCII ("the License"). You may not use */
/* this file except in compliance with the License. You may obtain a copy */
/* of the License by searching for "Sun Community Source License" on the */
/* World Wide Web at http://www.sun.com. See the License for the rights, */
/* obligations, and limitations governing use of the contents of this file. */
/* */
/* Sun Microsystems, Inc. has intellectual property rights relating to the */
/* technology embodied in these files. In particular, and without limitation, */
/* these intellectual property rights may include one or more U.S. patents, */
/* foreign patents, or pending applications. */
/* */
/* Sun, Sun Microsystems, the Sun logo, all Sun-based trademarks and logos, */
/* Solaris, Java and all Java-based trademarks and logos are trademarks or */
/* registered trademarks of Sun Microsystems, Inc. in the United States and */
/* other countries. microSPARC is a trademark or registered trademark of */
/* SPARC International, Inc. All SPARC trademarks are used under license and */
/* are trademarks or registered trademarks of SPARC International, Inc. in */
/* the United States and other countries. Products bearing SPARC trademarks */
/* are based upon an architecture developed by Sun Microsystems, Inc. */
/* */
/******************************************************************************/
/***************************************************************************
****************************************************************************
***
*** Program File: @(#)mc_icache.v
***
***
****************************************************************************
****************************************************************************/
// @(#)mc_icache.v 1.33 4/26/93
// This file contains the ICache SRAM Megacell Model
module mc_icache
(
it_di,
it_val_in,
it_cntx_in,
it_be,
it_be_vb,
it_be_cb,
it_acc_in,
// export_ic_scan_vec,
// import_it_scan_vec,
ic_hld,
ic_do,
ic_di,
ic_power_down,
ic_iiddtn,
it_power_down,
it_wle,
it_ain,
ic_ain,
ic_wle,
ic_be,
ic_scan_mode,
ic_scan_in,
ic_scan_out,
ic_tg_strobe,
ic_clk
);
input [31:13] it_di
;
input it_val_in
;
input [7:0] it_cntx_in
;
input it_be
;
input it_be_vb
;
input it_be_cb
;
input [4:0] it_acc_in
;
// input [65:0] import_it_scan_vec;
input [1:0] ic_hld
; // Synchronous hold asserted when "1"
input ic_power_down
; // Synchronous power down
input ic_iiddtn
;
input [(`ic_msb-3):0] ic_ain
;
input [63:0] ic_di
;
input ic_wle
;
input [1:0] ic_be
;
input ic_clk
;
input ic_scan_mode
;
input ic_scan_in
;
input ic_tg_strobe
;
// output [65:0] export_ic_scan_vec;
output [`ic_msb:5] it_ain
;
output it_wle
;
output it_power_down
;
output ic_scan_out
;
output [63:0] ic_do
;
wire [(`ic_msb-3):0] adr
, adr_in
;
wire logic_0
= 1'b0 ; // To suppress errors from $toggle tools
wire wle_in
, wle
;
wire powerdown_in
, powerdown
;
wire [1:0] be_in
, be
;
wire [63:0] di_in
, di
;
// Use this dummy bus to avoid port size mismatches but still
// allow addressing a 64KB cache in cache mode.
wor [(17-`log2_icachesize):1] ain_pad
; // [1:1] or [3:1]
// Mflipflop_noop_14 ain_reg({ain_pad,adr}, {ain_pad,adr_in}, ic_clk) ;
// Leave this out of scan. This is only for cache mode.
Mflipflop_noop_3 ain_pad_reg(ain_pad, ain_pad, ic_clk) ;
// 4 copies of this part of the address register.
Mflipflop_noop_4
ain_reg1(adr[3:0], adr_in[3:0], ic_clk) ;
// 2 copies of this part of the address register.
Mflipflop_noop_7
ain_reg2(adr[(`ic_msb-3):4], adr_in[(`ic_msb-3):4], ic_clk);
// 4 copies of this (32 x 2) bit register
Mflipflop_32 di_regh (di[63:32], di_in[63:32],
ic_clk, ic_hld[0]) ;
Mflipflop_32 di_regl (di[31:0], di_in[31:0],
ic_clk, ic_hld[1]) ;
// 2 copies
Mflipflop_noop ic_wle_reg (wle, wle_in, ic_clk) ;
// 6 copies
Mflipflop_noop
ic_pd_reg (powerdown, powerdown_in, ic_clk) ;
// 16 copies !!
Mflipflop_noop_2 ic_be_reg (be[1:0], be_in[1:0], ic_clk);
wire ic_scan_out;
assign it_wle = wle ;
assign it_power_down = powerdown ;
// ITags do not need the 2 lsb's of the address.
assign it_ain[`ic_msb:5] = adr[(`ic_msb-3):2] ;
wire [63:0] ic_do, do
;
assign ic_do[63:32] =
be[0] ? di[63:32] : ( do[63:32] ) ;
assign ic_do[31:0] =
be[1] ? di[31:0] : ( do[31:0] ) ;
// Icache Read/Write cycle
wire we_ctrl
= wle & ~ic_scan_mode & ~powerdown ;
wire [63:0] di_int
=
di ;
wire iram_clk
= ic_clk & ic_tg_strobe;
wire one
= 1'b1;
wire [1:0] we
= {2{we_ctrl}} & be[1:0] ;
wire [1:0] wep
= ~( {~(we[1] & ~iram_clk), ~(we[0] & ~iram_clk)} );
// Added to shut off the iram during power down or IDDQ test
// fix for rel 1.0
wire ic_iiddtn_
= ~ ic_iiddtn;
// wire shutoff_iram = powerdown | ic_iiddtn ;
wire shutoff_iram
= ~(powerdown | ic_iiddtn_) ;
/*
RR2048X64 iram (
.DO63(do[63]),
.DO62(do[62]),
.DO61(do[61]),
.DO60(do[60]),
.DO59(do[59]),
.DO58(do[58]),
.DO57(do[57]),
.DO56(do[56]),
.DO55(do[55]),
.DO54(do[54]),
.DO53(do[53]),
.DO52(do[52]),
.DO51(do[51]),
.DO50(do[50]),
.DO49(do[49]),
.DO48(do[48]),
.DO47(do[47]),
.DO46(do[46]),
.DO45(do[45]),
.DO44(do[44]),
.DO43(do[43]),
.DO42(do[42]),
.DO41(do[41]),
.DO40(do[40]),
.DO39(do[39]),
.DO38(do[38]),
.DO37(do[37]),
.DO36(do[36]),
.DO35(do[35]),
.DO34(do[34]),
.DO33(do[33]),
.DO32(do[32]),
.DO31(do[31]),
.DO30(do[30]),
.DO29(do[29]),
.DO28(do[28]),
.DO27(do[27]),
.DO26(do[26]),
.DO25(do[25]),
.DO24(do[24]),
.DO23(do[23]),
.DO22(do[22]),
.DO21(do[21]),
.DO20(do[20]),
.DO19(do[19]),
.DO18(do[18]),
.DO17(do[17]),
.DO16(do[16]),
.DO15(do[15]),
.DO14(do[14]),
.DO13(do[13]),
.DO12(do[12]),
.DO11(do[11]),
.DO10(do[10]),
.DO9(do[09]),
.DO8(do[08]),
.DO7(do[07]),
.DO6(do[06]),
.DO5(do[05]),
.DO4(do[04]),
.DO3(do[03]),
.DO2(do[02]),
.DO1(do[01]),
.DO0(do[00]),
.WE63(wep[0]),
.WE62(wep[0]),
.WE61(wep[0]),
.WE60(wep[0]),
.WE59(wep[0]),
.WE58(wep[0]),
.WE57(wep[0]),
.WE56(wep[0]),
.WE55(wep[0]),
.WE54(wep[0]),
.WE53(wep[0]),
.WE52(wep[0]),
.WE51(wep[0]),
.WE50(wep[0]),
.WE49(wep[0]),
.WE48(wep[0]),
.WE47(wep[0]),
.WE46(wep[0]),
.WE45(wep[0]),
.WE44(wep[0]),
.WE43(wep[0]),
.WE42(wep[0]),
.WE41(wep[0]),
.WE40(wep[0]),
.WE39(wep[0]),
.WE38(wep[0]),
.WE37(wep[0]),
.WE36(wep[0]),
.WE35(wep[0]),
.WE34(wep[0]),
.WE33(wep[0]),
.WE32(wep[0]),
.WE31(wep[1]),
.WE30(wep[1]),
.WE29(wep[1]),
.WE28(wep[1]),
.WE27(wep[1]),
.WE26(wep[1]),
.WE25(wep[1]),
.WE24(wep[1]),
.WE23(wep[1]),
.WE22(wep[1]),
.WE21(wep[1]),
.WE20(wep[1]),
.WE19(wep[1]),
.WE18(wep[1]),
.WE17(wep[1]),
.WE16(wep[1]),
.WE15(wep[1]),
.WE14(wep[1]),
.WE13(wep[1]),
.WE12(wep[1]),
.WE11(wep[1]),
.WE10(wep[1]),
.WE9(wep[1]),
.WE8(wep[1]),
.WE7(wep[1]),
.WE6(wep[1]),
.WE5(wep[1]),
.WE4(wep[1]),
.WE3(wep[1]),
.WE2(wep[1]),
.WE1(wep[1]),
.WE0(wep[1]),
//.CS(one),
.CS(shutoff_iram),
.OE63(one),
.OE62(one),
.OE61(one),
.OE60(one),
.OE59(one),
.OE58(one),
.OE57(one),
.OE56(one),
.OE55(one),
.OE54(one),
.OE53(one),
.OE52(one),
.OE51(one),
.OE50(one),
.OE49(one),
.OE48(one),
.OE47(one),
.OE46(one),
.OE45(one),
.OE44(one),
.OE43(one),
.OE42(one),
.OE41(one),
.OE40(one),
.OE39(one),
.OE38(one),
.OE37(one),
.OE36(one),
.OE35(one),
.OE34(one),
.OE33(one),
.OE32(one),
.OE31(one),
.OE30(one),
.OE29(one),
.OE28(one),
.OE27(one),
.OE26(one),
.OE25(one),
.OE24(one),
.OE23(one),
.OE22(one),
.OE21(one),
.OE20(one),
.OE19(one),
.OE18(one),
.OE17(one),
.OE16(one),
.OE15(one),
.OE14(one),
.OE13(one),
.OE12(one),
.OE11(one),
.OE10(one),
.OE9(one),
.OE8(one),
.OE7(one),
.OE6(one),
.OE5(one),
.OE4(one),
.OE3(one),
.OE2(one),
.OE1(one),
.OE0(one),
.DI63(di_int[63]),
.DI62(di_int[62]),
.DI61(di_int[61]),
.DI60(di_int[60]),
.DI59(di_int[59]),
.DI58(di_int[58]),
.DI57(di_int[57]),
.DI56(di_int[56]),
.DI55(di_int[55]),
.DI54(di_int[54]),
.DI53(di_int[53]),
.DI52(di_int[52]),
.DI51(di_int[51]),
.DI50(di_int[50]),
.DI49(di_int[49]),
.DI48(di_int[48]),
.DI47(di_int[47]),
.DI46(di_int[46]),
.DI45(di_int[45]),
.DI44(di_int[44]),
.DI43(di_int[43]),
.DI42(di_int[42]),
.DI41(di_int[41]),
.DI40(di_int[40]),
.DI39(di_int[39]),
.DI38(di_int[38]),
.DI37(di_int[37]),
.DI36(di_int[36]),
.DI35(di_int[35]),
.DI34(di_int[34]),
.DI33(di_int[33]),
.DI32(di_int[32]),
.DI31(di_int[31]),
.DI30(di_int[30]),
.DI29(di_int[29]),
.DI28(di_int[28]),
.DI27(di_int[27]),
.DI26(di_int[26]),
.DI25(di_int[25]),
.DI24(di_int[24]),
.DI23(di_int[23]),
.DI22(di_int[22]),
.DI21(di_int[21]),
.DI20(di_int[20]),
.DI19(di_int[19]),
.DI18(di_int[18]),
.DI17(di_int[17]),
.DI16(di_int[16]),
.DI15(di_int[15]),
.DI14(di_int[14]),
.DI13(di_int[13]),
.DI12(di_int[12]),
.DI11(di_int[11]),
.DI10(di_int[10]),
.DI9(di_int[09]),
.DI8(di_int[08]),
.DI7(di_int[07]),
.DI6(di_int[06]),
.DI5(di_int[05]),
.DI4(di_int[04]),
.DI3(di_int[03]),
.DI2(di_int[02]),
.DI1(di_int[01]),
.DI0(di_int[00]),
.ADR10(adr[10]),
.ADR9(adr[09]),
.ADR8(adr[08]),
.ADR7(adr[07]),
.ADR6(adr[06]),
.ADR5(adr[05]),
.ADR4(adr[04]),
.ADR3(adr[03]),
.ADR2(adr[02]),
.ADR1(adr[01]),
.ADR0(adr[00]));
*/
icache_ram iram ( .dout(do[63:0]),
.din(di_int[63:0]),
.ain(adr[10:0]),
.bw({{32{wep[0]}},{32{wep[1]}}})
);
assign
{ adr_in, wle_in, be_in, powerdown_in, di_in } =
{ ic_ain, ic_wle, ic_be, ic_power_down, ic_di} ;
endmodule
This page: |
Created: | Thu Aug 19 12:01:05 1999 |
| From: |
../../../sparc_v8/ssparc/caches/mc_i_tag_cache/rtl/mc_icache.v
|