// else if(`ssparc_core.sb_ack_l == 'h4)
			//	last_complete = Mclocks.cycle_count ;

			// stop simulation after bad trap, to stop queueed dvma xaction (810:asm2ver, use 910: for sbc & iom diag)
			else if(trap_tt_reg == 'h910) begin

				Mclocks.end_run = 1;
				Mclocks.end_run_error = 1;
				$display;
			        $display("*** BAD TRAP 0x%h DETECTED at 0x%x in cycle %d", trap_tt_reg, {pc,2'b00}, Mclocks.cycle_count);
			end

			// No completion this cycle - test for hang
			else if (Mclocks.cycle_count-last_complete
				    > cycle_limit) begin
				Mclocks.end_run = 1;
				Mclocks.end_run_error = 1;
				$display;
			        $display("*** HANG DETECTED at 0x%x in cycle %d",
					{pc,2'b00}, Mclocks.cycle_count);
                                $display("*** Hang error conditions - ic_miss=%b, dc_miss=%b, iu_pipe_hold=%b, mc_mbsy=%b, wb_empty=%b",
                                        ic_miss,
                                        dc_miss,
                                        hold,
                                        `rl_memif.mc_mbsy,
                                        wb_empty);
`ifdef MMU_GATE_LEVEL
`else
                                $display("*** Hang error conditions - m_state=%h, par_state=%s, mem_arb_state=%s",
                                        `m_mmu_cntl.marb_sm.m_state,
                                        `m_mmu_cntl.par_cntl.par_state_name,
                                        `m_mmu_cntl.marb_sm.state_name);
`endif

			end
		end
	end

// END A DIAGNOSTIC

	// The following code will set the end_run flag to stop
	// simulation when the end_diagnostic signal becomes active.
	// This signal is activated when an infinite loop branch
	// is seen in the WRITE cycle.
	// We delay setting end_run if there is store to memory pending
	//     (tracing is suspended when end_diag is on).
	// If random I/O is present in the system, vsc_dma_done will
	// be 0 until all I/O is halted, in order to ensure consistency
	// between Verilog and MPSAS.

	tri1 vsc_dma_done ;		// default state is 1

	wire store_pending = 1'b0;
//	    Msystem.ssparc.ssparc_mmu.mmusimtask.dc_wrbuf_pend
//	    | Msystem.ssparc.mc_mbsy
//	    | ~Msystem.ssparc.mc_mwe_l
//	    ;

	// NOTE - want end_run to be set if all of the conditions
	// below are met including that hold is 0 or x (eg: !==1).

	wire end_run_raw =
	    ~`Mdecode.ss_reset & ~scan_mode & `rl_dc_cntl.dcc_miss_idle
		& ~hold & end_diag & wb_empty & ~`rl_memif.mc_mbsy &
		vsc_dma_done ;
	wire end_run = (end_run_raw!==0) ;
	wire end_run_unknown = (end_run_raw===1'bx) ;

/*
 * Transmit end run status and end of run up to clocks module.
 */
	always @(posedge end_run)	//added posedge -
	begin
	    #1;				//added delay -
	    Mclocks.end_run = end_run ;
	    Mclocks.end_run_error = (end_diag_error|end_run_unknown) ;
	    if (end_run_unknown) 
		$display("*** unknowns %t: ss_reset=%b, scan_mode=%b, dcc_miss_idle=%b, hold=%b,\n***	end_diag=%b, wb_empty=%b, mc_mbsy=%b, sb_cpend=%b, vsc_dma_done=%b",
	    $realtime, `Mdecode.ss_reset, scan_mode, `rl_dc_cntl.dcc_miss_idle,
		hold, end_diag, wb_empty, `rl_memif.mc_mbsy,
		1'b1, vsc_dma_done) ;
	end

	// Stop the test if an error is counted
	reg end_on_error ; initial end_on_error = 1 ;
	always @(Mclocks.error_count)
	if (end_on_error && trace && (Mclocks.error_count>0)) begin
	    Mclocks.end_run = 1'b1 ;
	    Mclocks.end_run_error = 1'b1 ;
	end

// This garbage is for reset and DP MUX select checking.  this
// is so we don't start checking until the IU has done its
// first fetch

	wire post_reset =
		`Mdecode.pc_cntl.sel_post_reset;
	reg ppr; 
	reg [(1)-1:0] ppr_regmaster; always @ (posedge (clock )) begin if ((hold)===1'b0) ppr_regmaster = post_reset; else if ((hold)===1'b1) ppr_regmaster = ppr; else ppr_regmaster = 65'bx; if((clock) === 1'bx) #1 ppr = 65'bx; else #1 ppr = ppr_regmaster; end

endmodule