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Signals index

V
 V : Mccgen : wire
 vaf_en_hld : dp_mmu : input
Connects down to:MflipflopR_18:va_field_en_ff_18:enable_l 
Connects up to:mmu:MMU_dp:vaf_en_hld 
 vaf_en_hld : mmu : wire
Connects down to:m_mmu_cntl:MMU_cntl:vaf_en_hld , dp_mmu:MMU_dp:vaf_en_hld 
 vaf_en_hld : m_mmu_cntl : output
Connects down to:rl_mmu_regs:mmu_regs:vaf_en_hld 
Connects up to:mmu:MMU_cntl:vaf_en_hld 
 vaf_en_hld : rl_mmu_regs : output
Connects up to:m_mmu_cntl:mmu_regs:vaf_en_hld 
 valid : CAM_LINE : wire
Connects down to:MflipflopR_1:cam_line_v_1:out 
 valid : IOCAM_LINE : wire
Connects down to:MflipflopR_1:cam_line_v_1:out 
 valid_d : ssparc_core : wire
Connects down to:Miu:iu:valid_decode , fpufpc:ssparc_fpu:ext_valid_decode 
 valid_decode : Malu_control : input
Connects up to:Mdecode:alu_control:valid_decode 
 valid_decode : Mdata_byp1_1 : input
Connects up to:Mdecode:data_byp1_1:valid_decode 
 valid_decode : Mdata_byp2 : input
Connects up to:Mdecode:data_byp2:valid_decode 
 valid_decode : Mdcache_control : input
Connects up to:Mdecode:dcache_control:valid_decode 
 valid_decode : Mdecode : output wire
Connects down to:Mpipec_im_id:pipec_im_id:valid_decode , Mpipec_br_vald:pipec_br_vald:valid_decode , Mpipec_help_ilock:pipec_help_ilock:valid_decode , Mir_control:ir_control:valid_decode , Mdata_byp1_1:data_byp1_1:valid_decode , Mdata_byp2:data_byp2:valid_decode , Malu_control:alu_control:valid_decode , Mpc_control:pc_control:valid_decode , Mspecial_reg_control:special_reg_control:valid_decode , Mdcache_control:dcache_control:valid_decode , Mtrap_detection:trap_detection:valid_decode , Mpc_cntl:pc_cntl:valid_decode 
Connects up to:Miuchip:decode:valid_decode 
 valid_decode : Mir_control : input
Connects up to:Mdecode:ir_control:valid_decode 
 valid_decode : Miu : output
Connects down to:Miuchip:iuchip:valid_decode 
Connects up to:ssparc_core:iu:valid_d 
 valid_decode : Miuchip : output
Connects down to:Mdecode:decode:valid_decode 
Connects up to:Miu:iuchip:valid_decode 
 valid_decode : Mpc_cntl : input
Connects up to:Mdecode:pc_cntl:valid_decode 
 valid_decode : Mpc_control : input
Connects up to:Mdecode:pc_control:valid_decode 
 valid_decode : Mpipec_br_vald : output
Connects up to:Mdecode:pipec_br_vald:valid_decode 
 valid_decode : Mpipec_help_ilock : input
Connects up to:Mdecode:pipec_help_ilock:valid_decode 
 valid_decode : Mpipec_im_id : input
Connects up to:Mdecode:pipec_im_id:valid_decode 
 valid_decode : Mspecial_reg_control : input
Connects up to:Mdecode:special_reg_control:valid_decode 
 valid_decode : Mtrap_detection : input
Connects up to:Mdecode:trap_detection:valid_decode 
 valid_decode_ : Mpipec_br_vald : wire
 valid_decode_nilock : Malu_control : input
Connects up to:Mdecode:alu_control:valid_decode_nilock 
 valid_decode_nilock : Mdecode : wire
Connects down to:Mpipec_im_id:pipec_im_id:valid_decode_nilock , Mpipec_br_vald:pipec_br_vald:valid_decode_nilock , Mpipec_help_ilock:pipec_help_ilock:valid_decode_nilock , Mir_control:ir_control:valid_decode_nilock , Malu_control:alu_control:valid_decode_nilock , Mspecial_reg_control:special_reg_control:valid_decode_nilock , Mpc_cntl:pc_cntl:valid_decode_nilock 
 valid_decode_nilock : Mir_control : input
Connects up to:Mdecode:ir_control:valid_decode_nilock 
 valid_decode_nilock : Mpc_cntl : input
Connects up to:Mdecode:pc_cntl:valid_decode_nilock 
 valid_decode_nilock : Mpipec_br_vald : output wire
Connects up to:Mdecode:pipec_br_vald:valid_decode_nilock 
 valid_decode_nilock : Mpipec_help_ilock : input
Connects up to:Mdecode:pipec_help_ilock:valid_decode_nilock 
 valid_decode_nilock : Mpipec_im_id : input
Connects up to:Mdecode:pipec_im_id:valid_decode_nilock 
 valid_decode_nilock : Mspecial_reg_control : input
Connects up to:Mdecode:special_reg_control:valid_decode_nilock 
 valid_decode_nilock_l : Mpipec_br_vald : wire
 valid_f : pcimaster : reg
 valid_f : pcislave : reg
 valid_in : CAM_LINE : wire
 valid_in : IOCAM_LINE : wire
 valid_l : abort_write_sm : input
Connects up to:afxmaster:aw_sm:valid_l 
 valid_l : afxmaster : input (used in @negedge)
Connects down to:abort_write_sm:aw_sm:valid_l , afxm_sm:afxm_sm1:valid_l 
Connects up to:pcic:afxm:valid_l 
 valid_l : afxm_sm : input
Connects up to:afxmaster:afxm_sm1:valid_l 
 valid_l : pcic : input (used in @negedge)
Connects down to:afxmaster:afxm:valid_l 
Connects up to:ssparc_core:ssparc_pcic:w_valid_l 
 valid_l : rl_dpc : input
Connects down to:rl_dpc_core:dpc_core:valid_l 
Connects up to:rl_memif_major:dpc:valid_l 
 valid_l : rl_dpc_cont : input
Connects up to:rl_dpc_logic:ctrl:valid_l 
 valid_l : rl_dpc_core : input
Connects down to:rl_dpc_logic:dpc_logic:valid_l 
Connects up to:rl_dpc:dpc_core:valid_l 
 valid_l : rl_dpc_logic : input
Connects down to:rl_dpc_cont:ctrl:valid_l 
Connects up to:rl_dpc_core:dpc_logic:valid_l 
 valid_l : rl_mcb : output
Connects down to:rl_mcb_lgc:mcb_lgc:valid_l 
Connects up to:rl_memif_major:mcb:valid_l 
 valid_l : rl_mcb_lgc : output
Connects down to:S_sr_ff:ffsr_valid_srff:q 
Connects up to:rl_mcb:mcb_lgc:valid_l 
 valid_l : rl_memif : output
Connects down to:rl_memif_major:memif_major:valid_l 
Connects up to:ssparc_core:ssparc_memif:w_valid_l 
 valid_l : rl_memif_major : output
Connects down to:rl_mcb:mcb:valid_l , rl_dpc:dpc:valid_l 
Connects up to:rl_memif:memif_major:valid_l 
 valid_l1 : afxmaster : reg
 valid_l_dis : rl_mcb_lgc : wire
Connects down to:S_sr_ff:ffsr_valid_srff:en 
 valid_l_en : rl_mcb_lgc : wire
Connects down to:S_sr_ff:ffsr_valid_srff:dis 
 value : pcimaster_fm : reg
 val_in_w : mc_dtag : wire
Connects down to:Mflipflop_noop:val_in_reg:out 
 val_in_w : mc_itag : wire
Connects down to:Mflipflop_noop:val_in_reg:out 
 var_tbl : pcimaster_fm : reg
 var_tbl : pcislave_fm : reg
 var_tbl_counter : pcimaster_fm : integer
 var_tbl_counter : pcislave_fm : integer
 va_bp_hld : dp_mmu : input
Connects down to:MflipflopR_32:brk_pt_ff_32:enable_l 
Connects up to:mmu:MMU_dp:va_bp_hld 
 va_bp_hld : mmu : wire
Connects down to:m_mmu_cntl:MMU_cntl:va_bp_hld , dp_mmu:MMU_dp:va_bp_hld 
 va_bp_hld : m_mmu_cntl : output
Connects down to:rl_mmu_regs:mmu_regs:va_bp_hld 
Connects up to:mmu:MMU_cntl:va_bp_hld 
 va_bp_hld : rl_mmu_regs : output
Connects up to:m_mmu_cntl:mmu_regs:va_bp_hld 
 va_brkpt_mux : dp_mmu : wire
 va_field_en : dp_mmu : wire
Connects down to:MflipflopR_18:va_field_en_ff_18:out 
 va_fld_pad : dp_mmu : wire
 va_hit : rl_mmu_lgc : wire
 va_hit_a : dp_mmu : wire
 va_hit_b : dp_mmu : wire
 va_hit_c : dp_mmu : wire
 va_hit_d : dp_mmu : wire
 va_hit_e : dp_mmu : wire
 va_hit_f : dp_mmu : wire
 va_hit_g : dp_mmu : wire
 va_hit_h : dp_mmu : wire
 va_hit_i : dp_mmu : wire
 va_hit_j : dp_mmu : wire
 va_hit_k : dp_mmu : wire
 va_hit_l : dp_mmu : wire
 va_hit_m : dp_mmu : wire
 va_hit_n : dp_mmu : wire
 va_hit_r : dp_mmu : wire
 va_hit_s : dp_mmu : wire
 va_hit_t : dp_mmu : wire
 va_mux : dp_mmu : wire
 va_mux0_sel : dp_mmu : input
Connects up to:mmu:MMU_dp:va_mux0_sel 
 va_mux0_sel : mmu : wire
Connects down to:m_mmu_cntl:MMU_cntl:va_mux0_sel , dp_mmu:MMU_dp:va_mux0_sel 
 va_mux0_sel : m_mmu_cntl : output
Connects down to:rl_par_cntl:par_cntl:va_mux0_sel 
Connects up to:mmu:MMU_cntl:va_mux0_sel 
 va_mux0_sel : rl_par_cntl : output
Connects up to:m_mmu_cntl:par_cntl:va_mux0_sel 
 va_mux1_sel : dp_mmu : input
Connects up to:mmu:MMU_dp:va_mux1_sel 
 va_mux1_sel : mmu : wire
Connects down to:m_mmu_cntl:MMU_cntl:va_mux1_sel , dp_mmu:MMU_dp:va_mux1_sel 
 va_mux1_sel : m_mmu_cntl : output
Connects down to:rl_par_cntl:par_cntl:va_mux1_sel 
Connects up to:mmu:MMU_cntl:va_mux1_sel 
 va_mux1_sel : rl_par_cntl : output
Connects up to:m_mmu_cntl:par_cntl:va_mux1_sel 
 va_mux1_sel0 : rl_par_cntl : wire
 va_mux_adr_out : dp_mmu : wire
 va_mux_name : rl_par_cntl : reg
 va_mux_sel : dp_mmu : input
Connects up to:mmu:MMU_dp:va_mux_sel 
 va_mux_sel : mmu : wire
Connects down to:m_mmu_cntl:MMU_cntl:va_mux_sel , dp_mmu:MMU_dp:va_mux_sel 
 va_mux_sel : m_mmu_cntl : output
Connects down to:rl_par_cntl:par_cntl:va_mux_sel , rl_pa_mux:pa_muxl:va_mux_sel_1 , rl_pa_mux:pa_muxl:va_mux_sel_2 
Connects up to:mmu:MMU_cntl:va_mux_sel 
 va_mux_sel : rl_par_cntl : output
Connects up to:m_mmu_cntl:par_cntl:va_mux_sel 
 va_mux_sel_1 : rl_pa_mux : input
Connects up to:m_mmu_cntl:pa_muxl:va_mux_sel 
 va_mux_sel_2 : rl_pa_mux : input
Connects up to:m_mmu_cntl:pa_muxl:va_mux_sel 
 va_ptp4_sel : dp_mmu : input
Connects up to:mmu:MMU_dp:va_ptp4_sel 
 va_ptp4_sel : mmu : wire
Connects down to:m_mmu_cntl:MMU_cntl:va_ptp4_sel , dp_mmu:MMU_dp:va_ptp4_sel 
 va_ptp4_sel : m_mmu_cntl : output
Connects down to:rl_pa_mux:pa_muxl:va_ptp4_sel 
Connects up to:mmu:MMU_cntl:va_ptp4_sel 
 va_ptp4_sel : rl_pa_mux : output
Connects up to:m_mmu_cntl:pa_muxl:va_ptp4_sel 
 va_ptp8_sel : dp_mmu : input
Connects up to:mmu:MMU_dp:va_ptp8_sel 
 va_ptp8_sel : mmu : wire
Connects down to:m_mmu_cntl:MMU_cntl:va_ptp8_sel , dp_mmu:MMU_dp:va_ptp8_sel 
 va_ptp8_sel : m_mmu_cntl : output
Connects down to:rl_pa_mux:pa_muxl:va_ptp8_sel 
Connects up to:mmu:MMU_cntl:va_ptp8_sel 
 va_ptp8_sel : rl_pa_mux : output wire
Connects up to:m_mmu_cntl:pa_muxl:va_ptp8_sel 
 va_ptp_out : dp_mmu : wire
 va_range_err : rl_mmu_regs : wire
 va_sel_par_in : m_mmu_cntl : wire
Connects down to:rl_tw_sm:tw_sm:va_sel_par_in , rl_par_cntl:par_cntl:va_sel_par_in 
 va_sel_par_in : rl_par_cntl : input
Connects up to:m_mmu_cntl:par_cntl:va_sel_par_in 
 va_sel_par_in : rl_tw_sm : output
Connects up to:m_mmu_cntl:tw_sm:va_sel_par_in 
 va_src_sel : dp_mmu : input
Connects up to:mmu:MMU_dp:va_src_sel 
 va_src_sel : mmu : wire
Connects down to:m_mmu_cntl:MMU_cntl:va_src_sel , dp_mmu:MMU_dp:va_src_sel 
 va_src_sel : m_mmu_cntl : output
Connects down to:rl_mmu_regs:mmu_regs:va_src_sel 
Connects up to:mmu:MMU_cntl:va_src_sel 
 va_src_sel : rl_mmu_regs : output
Connects up to:m_mmu_cntl:mmu_regs:va_src_sel 
 va_s_in : mmu : wire
Connects down to:m_mmu_cntl:MMU_cntl:va_s_in , dp_mmu:MMU_dp:iva_s_in , dp_mmu:MMU_dp:dva_s_in 
 va_s_in : m_mmu_cntl : output
Connects down to:rl_tw_sm:tw_sm:va_s_in 
Connects up to:mmu:MMU_cntl:va_s_in 
 va_s_in : rl_tw_sm : output
Connects up to:m_mmu_cntl:tw_sm:va_s_in 
 va_tag_mux_out : dp_mmu : wire
 va_tag_out : dp_mmu : output wire
Connects up to:mmu:MMU_dp:tlb_tag_in 
 va_type_bp : rl_mmu_lgc : wire
 va_type_hit : rl_mmu_lgc : wire
 Vcc : rl_col_row_addr : wire
 vcd : Mccdisp : reg
 vcd_end : Mccdisp : integer
 vcd_start : Mccdisp : integer
 vco : pll : reg
 vc_gnt3_ : Msystem : wire
Connects down to:MASTER:pciM3:gnt_ 
 vc_req3_ : Msystem : wire
Connects down to:MASTER:pciM3:req_ 
 vdd : AdderLSBlog : wire
Connects down to:ME_TIEOFF:toff:VDD 
 vdd : AregLoadCtl : wire
Connects down to:ME_TIEOFF:toff:VDD , ME_NMUX2B_B:alcn0:a 
 vdd : BregLoadCtl : wire
Connects down to:ME_TIEOFF:toff:VDD , ME_NMUX2B_B:alcn0:a 
 vdd : CondMux : wire
Connects down to:ME_TIEOFF:toff:VDD 
 vdd : CSRegSlice : wire
Connects down to:ME_TIEOFF:toff:VDD , ME_NMUX_2B_58:iz:D0 , ME_NMUX_2B_58:iz:D0 , ME_NMUX_2B_58:iz:D0 , ME_NMUX_2B_58:iz:D0 , ME_NMUX_2B_58:iz:D0 , ME_NMUX_2B_58:iz:D0 , ME_NMUX_2B_58:iz:D0 , ME_NMUX_2B_58:iz:D0 , ME_NMUX_2B_58:iz:D0 , ME_NMUX_2B_58:iz:D0 , ME_NMUX_2B_58:iz:D0 , ME_NMUX_2B_58:iz:D0 , ME_NMUX_2B_58:iz:D0 , ME_NMUX_2B_58:iz:D0 , ME_NMUX_2B_58:iz:D0 , ME_NMUX_2B_58:iz:D0 , ME_NMUX_2B_58:iz:D0 , ME_NMUX_2B_58:iz:D0 , ME_NMUX_2B_58:iz:D0 , ME_NMUX_2B_58:iz:D0 , ME_NMUX_2B_58:iz:D0 , ME_NMUX_2B_58:iz:D0 , ME_NMUX_2B_58:iz:D0 , ME_NMUX_2B_58:iz:D0 , ME_NMUX_2B_58:iz:D0 , ME_NMUX_2B_58:iz:D0 , ME_NMUX_2B_58:iz:D0 , ME_NMUX_2B_58:iz:D0 , ME_NMUX_2B_58:iz:D0 , ME_NMUX_2B_58:iz:D0 , ME_NMUX_2B_58:iz:D0 , ME_NMUX_2B_58:iz:D0 , ME_NMUX_2B_58:iz:D0 , ME_NMUX_2B_58:iz:D0 , ME_NMUX_2B_58:iz:D0 , ME_NMUX_2B_58:iz:D0 , ME_NMUX_2B_58:iz:D0 , ME_NMUX_2B_58:iz:D0 , ME_NMUX_2B_58:iz:D0 , ME_NMUX_2B_58:iz:D0 , ME_NMUX_2B_58:iz:D0 , ME_NMUX_2B_58:iz:D0 , ME_NMUX_2B_58:iz:D0 , ME_NMUX_2B_58:iz:D0 , ME_NMUX_2B_58:iz:D0 , ME_NMUX_2B_58:iz:D0 , ME_NMUX_2B_58:iz:D0 , ME_NMUX_2B_58:iz:D0 , ME_NMUX_2B_58:iz:D0 , ME_NMUX_2B_58:iz:D0 , ME_NMUX_2B_58:iz:D0 , ME_NMUX_2B_58:iz:D0 , ME_NMUX_2B_58:iz:D0 , ME_NMUX_2B_58:iz:D0 , ME_NMUX_2B_58:iz:D0 , ME_NMUX_2B_58:iz:D0 , ME_NMUX_2B_58:iz:D0 , ME_NMUX_2B_58:iz:D0 , ME_NMUX_2B_58:iz:D1 
 VDD : expconstadd : wire
Connects down to:ME_TIEOFF:t1:VDD , add2:a0:cin 
 vdd : ExpRegLoadCtl : wire
Connects down to:ME_TIEOFF:toff:VDD , ME_NMUX2B:en1:b 
 VDD : fpm_exp : wire
Connects down to:ME_TIEOFF:t1:VDD 
 VDD : fpm_frac : wire
Connects down to:ME_TIEOFF:t1:VDD , ME_MUX3_53:opxmux:d0 , ME_MUX3_53:opxmux:d1 , ME_MUX3_53:opxmux:d2 , ME_MUX3_25:opymux_hi:d0 , ME_MUX3_25:opymux_hi:d1 , ME_MUX3_25:opymux_hi:d2 
 vdd : fp_ctl : wire
Connects down to:ME_TIEOFF:toff:VDD , Control:cl:Conditionals_14_8 
 vdd : fp_exp : wire
Connects down to:ME_TIEOFF:toff:VDD , ME_MUX_4B_13:Ymux:D1 
 vdd : fp_frac : wire
Connects down to:ME_TIEOFF:toff:VDD 
 vdd : fp_qst : wire
Connects down to:ME_TIEOFF:toff:VDD 
 VDD : ME_TIEOFF : output
Connects down to:N1Z001:vdd:O 
Connects up to:ShiftLeftCtl:toff:vdd , fp_qst:toff:vdd , CondMux:toff:vdd , BregLoadCtl:toff:vdd , expconstadd:t1:VDD , AdderLSBlog:toff:vdd , MIptr:toff:vdd , SignLogic:toff:vdd , fpm_frac:t1:VDD , fp_frac:toff:vdd , YMuxCtl:toff:vdd , AregLoadCtl:toff:vdd , ExpRegLoadCtl:toff:vdd , stat_ctl:toff:HI , ShiftLeft:toff:vdd , fp_ctl:toff:vdd , MISelect:toff:vdd , fp_exp:toff:vdd , CSRegSlice:toff:vdd , ResultException:toff:vdd , fpm_exp:t1:VDD 
 vdd : MIptr : wire
Connects down to:ME_TIEOFF:toff:VDD 
 vdd : MISelect : wire
Connects down to:ME_TIEOFF:toff:VDD , ME_NMUX2B:g5_2:a 
 vdd : Msystem : reg
 vdd : ResultException : wire
Connects down to:ME_TIEOFF:toff:VDD , ME_NMUX2B:zq1:a 
 Vdd : rl_dpc_logic : wire
Connects down to:parity_tree:par_lo_gen:enable , parity_tree:par_hi_gen:enable 
 vdd : ShiftLeft : wire
Connects down to:ME_TIEOFF:toff:VDD , ME_NMUX_2B_58:g24:D1 , ME_NMUX_2B_58:g24:D1 , ME_NMUX_2B_58:g24:D1 , ME_NMUX_2B_58:g24:D1 , ME_NMUX_2B_58:g26:D1 
 vdd : ShiftLeftCtl : wire
Connects down to:ME_TIEOFF:toff:VDD , ME_MUX2B:g22:b 
 vdd : SignLogic : wire
Connects down to:ME_TIEOFF:toff:VDD 
 vdd : YMuxCtl : wire
Connects down to:ME_TIEOFF:toff:VDD 
 vec_hdr_subloop : Mccdisp : integer
 vec_max_subloop : Mccdisp : integer
 vec_mcd : Mccdisp : integer
 vec_subloop : Mccdisp : integer
 vendor_id_reg : pcimaster_fm : reg
 virt_ptp2 : m_mmu_cntl : wire
Connects down to:rl_tw_sm:tw_sm:virt_ptp2 , rl_mmu_regs:mmu_regs:virt_ptp2 
 virt_ptp2 : rl_mmu_regs : output wire
Connects down to:MflipflopR_1:virt_ptp2_ff_1:out 
Connects up to:m_mmu_cntl:mmu_regs:virt_ptp2 
 virt_ptp2 : rl_tw_sm : input
Connects up to:m_mmu_cntl:tw_sm:virt_ptp2 
 vlt : pcimaster_flags : integer
 vlt : pcimonitor_flags : integer
 vlt : pcislave_flags : integer
 Vm : Micceval : wire
 VN : BZCMPS : input
 VN_1 : BZCMPS : input
 vptp_mode : cam : wire
 vptp_mode : iocam : wire
 vsc_dma_done : Mtrace : tri1
 vsh_nl : Mclocks : reg
 vss : Msystem : reg
ABCDEFGHIJKLMNOPQRSTUVWXYZ_
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