.CLK ( ss_clock ),
	.RST ( ss_reset ),
	.CO_IN ( tlb_co_in ),
	.CR ( tlb_c_rd )

// 	.SCM ( ss_scan_mode ),
// 	.SCN_IN ( mc_tlb_scan_in ),
// 	.TG_STROBE ( mm_tg_strobe ),
// 	.PDM ( standby_dsbl_tlb ),
// 	.SCN_OUT ( mc_tlb_scan_out )
	);


// Added spare cells

        spares  mmu_spares ();

/*************************************************************************/

/*************************************************************************/
/**                  TLB TAG hardware representation                    **/
/**                                                                     **/
/** PTE                                                                 **/
/**     +---+--+--------+--+-------+--+------+----------+-----+-+-+-+-+ **/
/**     | V |L1|  INDX1 |L2| INDX2 |L3| INDX3| Context  | PTCT|S|I|P|M| **/
/**     +---+--+--------+--+-------+--+------+----------+-----+-+-+-+-+ **/
/**      41  40 39    32 31 30   25 24 23  18 17      10 9   4 3 2 1 0  **/
/**                                                                     **/
/*************************************************************************/
/**                  TLB TAG software representation                    **/
/** PTE                                                                 **/
/**     +---------+-------+-------+-----------+---+-----+-----+-+-+-+-+ **/
/**     |  INDX1  | INDX2 | INDX3 |  Context  | V | LVL | PTCT|S|I|P|M| **/
/**     +---------+-------+-------+-----------+---+-----+-----+-+-+-+-+ **/
/**      41     34 33   28 27   22 21       14  13 12 10 9   4 3 2 1 0  **/
/**                                                                     **/
/*************************************************************************/
/** PTP                                                                 **/
/**     +-------------------------------------+---+-----+---+---+---+   **/
/**     |      Physical Tag  (PAR[27:02])     | V | LVL | S | IO| P |   **/
/**     +-------------------------------------+---+-----+---+---+---+   **/
/**      31                                  6  5  4   3  2   1   0     **/
/*************************************************************************/

/***** RE-assign tag output to match software model **********************/
    assign tlb_tag_out = {cd_out[39:32],
                          cd_out[30:25],
                          cd_out[23:18],
                          cd_out[17:10],
                          cd_out[41:40], cd_out[31], cd_out[24],
                          cd_out[09:00]};

//synopsys translate_off

	// dummy module used for simulation
//mmu_simtask mmusimtask();

//synopsys translate_on

endmodule