/******************************************************************************/
/* */
/* Copyright (c) 1999 Sun Microsystems, Inc. All rights reserved. */
/* */
/* The contents of this file are subject to the current version of the Sun */
/* Community Source License, microSPARCII ("the License"). You may not use */
/* this file except in compliance with the License. You may obtain a copy */
/* of the License by searching for "Sun Community Source License" on the */
/* World Wide Web at http://www.sun.com. See the License for the rights, */
/* obligations, and limitations governing use of the contents of this file. */
/* */
/* Sun Microsystems, Inc. has intellectual property rights relating to the */
/* technology embodied in these files. In particular, and without limitation, */
/* these intellectual property rights may include one or more U.S. patents, */
/* foreign patents, or pending applications. */
/* */
/* Sun, Sun Microsystems, the Sun logo, all Sun-based trademarks and logos, */
/* Solaris, Java and all Java-based trademarks and logos are trademarks or */
/* registered trademarks of Sun Microsystems, Inc. in the United States and */
/* other countries. microSPARC is a trademark or registered trademark of */
/* SPARC International, Inc. All SPARC trademarks are used under license and */
/* are trademarks or registered trademarks of SPARC International, Inc. in */
/* the United States and other countries. Products bearing SPARC trademarks */
/* are based upon an architecture developed by Sun Microsystems, Inc. */
/* */
/******************************************************************************/
/***************************************************************************
****************************************************************************
***
*** Program File: @(#)mmu.v
***
****************************************************************************
****************************************************************************/
// @(#)mmu.v 1.134 9/3/93
//******************************************************************************
// mmu.v
//
// Description:
// This module describes the MMU. It instantiates
// the MMU datapath models, and the MMU control. No
// logic is uniquely defined in this module. Only
// connections between the different modules are defined.
//
// Dependencies:
// This module is instantiated by the ssparc.v module?
//
//******************************************************************************
/* Changes:
changed TLB module name to be "S_TLB", to match with its
TLB Synopsys model.
Should have changed the name in its Snopsys model.
*/
![[Up: ssparc_core ssparc_mmu]](v2html-up.gif)
module mmu
(
enbl_br_fold, // enable for branch folding
// mm_ifetch, // ifetch from sbus (EPROM)
mm_mdata_en0, // tri-state enable for DPC word 0
mm_issue_req_early, // signal to memif of a pending mm_issue_req
mm_dacc_err, // output data access parity error
mm_dacc_exc, // output data access exception
mm_dacc_miss, // output data access xlate miss
mm_dacc_wp, // output data access watchpoint trap
mm_bp_dtct, // output MMU breakpoint detect
mm_misc2cf, // misc to cfb for PIO ld
mm_misc2cf_2nd, /* transfer misc to cachefill (MEMIF) 2nd word */
mm_hold_rst, // hold watch dog reset
mm_pa, // output of Physical Address
cxr, // output of current context
mm_caddr, // CAS address (virtual) to MCB
mm_mreq, // memory request type to mcb
mm_fb_req, // memory FB request
mm_fb_size, // memory FB request size
mm_fb_page, // memory FB request page mode
mm_page, // dram page mode indicator
// mm_slock, // indicates iu requires exclusive use of sbus
mm_oddpar, // reflects PCR control
mm_parity_en, // reflects PCR control
mm_rfr_cntl, // reflects PCT control
// mm_sb_pa, // PA for sbc
// mm_iodaten, // indicates data to be driven from sbc
// mm_iostben, // assert stb_en for sbc
// mm_pa_valid, // PA valid for SBC
// mm_sbsize, // SB size field indicating size of operation
// mm_cpcyc_stb_l, // output indicating that data & addr. valid
// mm_cpsb_wrt, // output indicating CP to SB write.
// mm_sb_pe, // indicates a parity error during an IO DMA
// mm_sbae, // reflects PCR sbus arbitration enable
mm_sbae_0, // reflects PCR sbus arbitration enable
mm_rom_module_speed,
// mm_sscr_ba8, // reflects SSCR transfer size
mm_lvl15_int_l, // Level-15 interrupt output
mm_issue_req,
mm_issue_req2,
misc, // mdata output bus
precharge_early_0, // add precharge early
precharge_early_1,
mm_istat_avail,
mm_dstat_avail,
mm_dcdaten_in,
mm_icdaten,
mm_dct_daten,
mm_wbstb,
mm_wbsel1,
mm_icache_enbl,
mm_dcache_enbl,
mm_cache_stat,
mm_dabort,
mm_dcstben,
mm_icstben,
mm_iabort,
icstben_asi,
mm_fs_lvl,
mm_fs_perr,
mm_fs_iae,
mm_fs_xerr,
mm_fs_mmiss,
mm_fs_sbe,
mm_fs_sto,
mm_fs_sptct,
mm_mem_dbg,
pcic_ifetch,
mm_go_standby,
// inputs
turn_off_standby,
afx_rst_page_vld,
bm_sel,
// falcon_exists,
w_sp_sel, // Speed select (for mmu status)
w_div_ctl, // Divide by cntl (mmu status)
mc_afx_to, // AFX timeout indicator
ic_idle, // icache idle indicater
mc_refresh, // d ram refresh
ic_miss_sustain,
it_hit_f , // itag hit in f stage ** ASSERTED LOW **
// Net name was not change for hand edit
// Actually connected to it_hit_f_mmu at top level
ic_miss_or_part ,
ic_miss_and_part ,
dc_miss_or_part,
dc_miss_and_part,
dt_hit_w,
dc_miss_sustain,
invalid_wb_entry,
wb_valid,
wb0_hold_lo,
wb1_hold_lo,
wb2_hold_lo,
wb3_hold_lo,
wb_1_sel,
wb_2_sel,
wb_3_sel,
misc_in, // mdata input bus
iu_pipe_hold, //
pipe_hold4mmu_dp, // pip hold for dp_mmu
iu_size_e, // input indicating size of iu mem op in e stage
iu_asi_e, // input indicating asi in e stage
ld_op_e, // input indicating read req pending
st_op_e, // input indicating write req pending
fpu_mem_e, // indicates fpu mem op in E-stage
fp_trap_fix, // FPU trap may occur at anytime
iu_iva_g, // input of instruction virtual address
iu_dva_e, // input of data virtual address
mc_mstb_l, // input mdata strobe from mcb
mc_mbsy, // input mcb busy indicator
dp_perr, // input from dpc indicating parity error
// sb_ioa, // IO address input bus
// sb_cyc_pnd, // input indicating an SB cycle pending
// sb_sbslot, // Sbus slot ID for current SB cycle
// sb_ioreq, // encoded IO request
// sb_errsize, // indicates size of op in which error occrd
// sb_err_type, // SB error type (2-bits)
// sb_write_error, // CPU write error to SBC
// sb_va_val_l, // Hold enable for io_addr reg.
iu_in_trap, // iu in trap condition
mm_tg_strobe,
// sb_ioreq_vld,
mc_caddr_hld,
iu_sfs_sup,
iu_sfs_perr,
iu_sfs_xerr,
iu_sfs_mmiss,
iu_sfs_iae,
iu_sfs_sbe,
iu_sfs_sto,
iu_sfs_prtct,
iu_sfs_priv,
iu_sfs_lvl,
iu_mm_iacc_wp_exc_d,
dcc_idle,
ihold_d1, // MMU perf counter trigger
dhold_d1, // MMU perf counter trigger
dc_shold, // MMU perf counter trigger
did_fetch, // MMU perf counter trigger
fhold_d1, // MMU perf counter trigger
fhold_fqfull_d1, // MMU perf counter trigger
iu_sup_mode, // MMU perf counter trigger
ss_reset,
ss_reset_any,
ss_scan_mode,
mc_tlb_scan_in,
m_mmu_cache_scan_out,
standby_dsbl_tlb,
mem_idle, // mem idle just before standby mode
hold_fetch_f_l, // F-stage signal that holds fetch logic
p_reply_dec, // AFX queue status
ss_clock
);
/** Outputs for interfacing with the -IU- ****************************/
output mm_mdata_en0; // tri-state enable for DPC word 0
output mm_dacc_err; // output data access parity error
output mm_dacc_exc; // output data access exception
output mm_dacc_miss; // output data access xlate miss
output mm_dacc_wp; // output data access watchpoint trap
output mm_bp_dtct; // output MMU breakpoint detect
output mm_misc2cf; //c to cfb for pio ld
output mm_misc2cf_2nd; /* transfer misc to cachefill (MEMIF) 2nd word */
output enbl_br_fold; // enable for branch folding
/*** added ******/
output mm_hold_rst; // hold watch dog reset
/** Outputs for interfacing with the -MCB/DPC- ****************************/
output [30:00] mm_pa; // output of Physical Address
output [11:3] mm_caddr; // CAS address (virtual) to MCB
output [3:0] mm_mreq; // memory request type to mcb
output mm_fb_req; // memory FB request
output [1:0] mm_fb_size; // memory FB request size
output mm_fb_page; // memory FB request page mode
output mm_page; // dram page mode indicator
output mm_oddpar; // reflects PCR control
output mm_parity_en; // reflects PCR control
output [3:0] mm_rfr_cntl; // reflects PCT control
output mm_issue_req; // issue mem request
output mm_issue_req2; // issue mem request (copy)
/** Outputs for interfacing with the -SBC- ****************************/
wire [30:00] mm_sb_pa; // output pa to sbc
// output mm_iodaten; // indicates data to be driven from sbc
// output mm_ifetch; // ifetch from sbus (EPROM)
output mm_issue_req_early; // signal to memif of a pending issue_req
// output mm_iostben; // assert stb_en for sbc
// output mm_pa_valid; // PA vaild for SBC
// output [1:0] mm_sbsize; // SB size field indicating size of operation
// output mm_cpcyc_stb_l; // output indicating that data & addr. valid
// output mm_cpsb_wrt; // output indicating CP to SB write.
// output mm_sb_pe; // indicates a parity error during an IO DMA
// output [5:0] mm_sbae; // reflects PCR sbus arbitration enable
output mm_sbae_0;
output [3:0] mm_rom_module_speed;
// output [4:0] mm_sscr_ba8; // reflects SSCR transfer size
// output mm_slock; // indicates iu requires exclusive use of sbus
/** Misc. Outputs *************************************************************/
output mm_lvl15_int_l; // Level-15 interrupt
output m_mmu_cache_scan_out; // scan out
output [31:00] misc; // mdata output bus
output [7:0] cxr; // mdata output bus
output precharge_early_0;
output precharge_early_1;
output mm_istat_avail;
output mm_dstat_avail;
output mm_dcdaten_in;
output mm_icdaten;
output mm_dct_daten;
output mm_wbstb;
output mm_wbsel1;
output mm_icache_enbl;
output mm_dcache_enbl;
output mm_cache_stat;
output mm_dabort ;
output mm_dcstben ;
output mm_icstben ;
output mm_iabort ;
output icstben_asi ;
output [1:0] mm_fs_lvl; // Instruction Fault status PTE level
output [1:0] mm_fs_perr; // Instruction Fault status TW perr
output mm_fs_iae; // Instr Fault Invalid Address Error
output mm_fs_xerr; // Instr Fault translation error
output mm_fs_mmiss; // Instr Fault TLB miss (software tw)
output mm_fs_sbe; // Instr Fault Sbus Error
output mm_fs_sto; // Instr Fault Sbus timeout
output mm_fs_sptct; // Instr Fault protection exception
output [1:0] mm_mem_dbg; // Memory access debug signals
output pcic_ifetch; // for pci boot
wire pcic_ifetch; // for pci boot
output mm_go_standby; // for programmable standby
wire mm_go_standby; // for programmable standby
input turn_off_standby; // reset the mm_go_standby bit
input afx_rst_page_vld; // reset the page valid bits
input [1:0] bm_sel; // BOOTMODE select (1/0) = (SBus/AFX)
// input falcon_exists;
input [2:0] w_sp_sel; // Speed select (for mmu status)
input [1:0] w_div_ctl; // Divide by cntl (mmu status)
input mc_afx_to; /* AFX timeout indicator */
input ic_idle; // icache is idle
input mc_refresh; // d ram refresh
input [1:0] wb_valid;
input invalid_wb_entry;
input wb0_hold_lo, wb1_hold_lo, wb2_hold_lo, wb3_hold_lo;
input wb_1_sel, wb_2_sel, wb_3_sel;
input [31:00] misc_in; // mdata input bus
/******************************************************************************/
/** Inputs for interfacing with the -IU- ****************************/
input iu_pipe_hold; // indicates iu is holding pipeline
input pipe_hold4mmu_dp; // pipe hold signal for dp_mmu
input [1:0] iu_size_e; // input indicating size of iu mem op in e stage
input [5:0] iu_asi_e; // input indicating asi in e stage
input ld_op_e; // input indicating read req pending
input st_op_e; // input indicating write req pending
input fpu_mem_e; // indicates fpu mem op in E-stage
input fp_trap_fix; // FPU trap may occur at anytime
input [31:02] iu_iva_g; // input of instruction virtual address
input [31:00] iu_dva_e; // input of data virtual address
/** Inputs for interfacing with the I$ ***************************************/
input ic_miss_sustain; // I$ miss sustain signal from I$ control
input ic_miss_or_part; // I$ miss signal from D$ control
input ic_miss_and_part; // I$ miss signal from D$ control
input dc_miss_or_part; // D$ miss signal from D$ control
input dc_miss_and_part; // D$ miss signal from D$ control
input dt_hit_w; // D$ miss signal from D$ control
input it_hit_f; // itag hit in f stage ** ASSERTED LOW **
input dc_miss_sustain; // D$ miss sustain signal from D$ control
/** Inputs for interfacing with the -MCB/DPC- ****************************/
input mc_mstb_l; // input mdata strobe from mcb
input mc_mbsy; // input mcb busy indicator
input [1:0] dp_perr; // input from dpc indicating parity error
/** Inputs for interfacing with the -SBC- ****************************/
// input [31:00] sb_ioa; // IO address input bus
// input sb_cyc_pnd; // input indicating an SB cycle pending
// input [2:0] sb_sbslot; // Sbus slot ID for current SB cycle
// input [3:0] sb_ioreq; // encoded IO request
// input [2:0] sb_errsize; // indicates size of op in which error occrd
// input [1:0] sb_err_type; // SBC error type
// input sb_write_error; // CPU write error to SBC
// input sb_va_val_l; // Hold enable for the io_addr register in dp_mmu
/** Misc. Inputs *************************************************************/
input iu_in_trap; // indicates iu in trap condition
// input sb_ioreq_vld;
input mc_caddr_hld; // mc caddr hold
input iu_sfs_sup; // IU fault status supervisor bit
input [1:0] iu_sfs_perr; // IU fault status Parity error
input iu_sfs_xerr; // IU fault status translation error
input iu_sfs_mmiss; // IU fault status TLB miss (software tw)
input iu_sfs_iae; // IU fault status Invalid Address Error
input iu_sfs_sbe; // IU fault status Sbus error
input iu_sfs_sto; // IU fault status Sbus timeout
input iu_sfs_prtct; // IU fault status protection exception
input iu_sfs_priv; // IU fault status privilege exception
input [1:0] iu_sfs_lvl; // IU fault status PTE level field
input iu_mm_iacc_wp_exc_d; // IU instr watchpoint trap trigger
input dcc_idle; // D$ state machine is IDLE
input ihold_d1; // MMU perf counter trigger
input dhold_d1; // MMU perf counter trigger
input dc_shold; // MMU perf counter trigger
input did_fetch; // MMU perf counter trigger
input fhold_d1; // MMU perf counter trigger
input fhold_fqfull_d1; // MMU perf counter trigger
input iu_sup_mode; // MMU perf counter trigger
input standby_dsbl_tlb; // tell tlb for Power down mode
input mem_idle; // mem idle just before standby mode
input hold_fetch_f_l; // F-stage signal that holds fetch logic
input [2:0] p_reply_dec; // AFX queue status (# of entries)
input ss_clock; // supply 1 main system clock
input ss_reset;
input ss_reset_any;
input ss_scan_mode;
input mc_tlb_scan_in;
input mm_tg_strobe;
/******************************************************************************/
// synopsys translate_off
`ifdef MMU_GATE_LEVEL
`else
wire [31:0] pcr = MMU_cntl.mmu_regs.mmu_cr ;
`endif
wire[31:0] mmu_count;
assign mmu_count = Mclocks.cycle_count;
wire[63:0] cfb;
assign cfb = `SSPARC_CORE.cache_fill;
// synopsys translate_on
/******************************************************************************/
/******************************************************************************/
/** Connecting scan statements *********************************************/
wire m_mmu_cache_scan_out; // MMU_cache scan output
wire dp_mmu_scan_out; // dp_mmu scan output
wire mc_tlb_scan_in; // mc_tlb scan input
wire mc_tlb_scan_out; // mc_tlb scan output
/** Bus interconnects **/
wire [1:0] wb_3_size;
wire [1:0] mm_fb_size;
wire [1:0] wb_3_asi;
wire [1:0] tw_sm_lvl;
wire [2:0] tlb_ram_lvl;
wire [2:0] tlb_cam_lvl;
wire [2:0] access_type;
wire [12:2] r_d_vaddr_out;
wire mm_dva_8_w = r_d_vaddr_out[8] ;
wire [2:0] mbit_sel;
wire [5:0] tlb_acc_cmp;
wire [3:0] va_mux0_sel;
wire [4:0] va_mux1_sel;
wire [3:0] va_mux_sel;
wire [1:0] bp_sel_30;
wire [1:0] bp_sel_28;
wire [1:0] bp_sel_20;
wire [1:0] bp_sel_19;
wire [1:0] bp_sel_18;
wire [1:0] bp_sel_17;
wire [1:0] bp_sel_16;
wire [1:0] bp_sel_15;
wire [1:0] bp_sel_14;
wire [3:0] va_ptp4_sel;
wire [4:0] dp_mux1_sel;
wire [4:0] pamux_rd_sel;
wire [5:0] tlb_addr;
wire [41:00] tlb_tag_in;
wire [41:00] tlb_tag_out;
wire [31:00] pa_mux_rd;
wire [27:00] tlb_data_in;
wire [27:00] tb_out;
wire [41:00] cd_out;
wire [1:0] par_sel;
wire [1:0] mm_page_hit_en;
wire [1:0] va_src_sel;
/* */
/******************************************************************************/
/** Module instantiations *********************************************/
/******************************************************************************/
m_mmu_cntl MMU_cntl(
.ic_miss (ic_miss),
.enbl_br_fold (enbl_br_fold),
// .mm_ifetch (mm_ifetch),
.mm_page_hit_en (mm_page_hit_en),
.mm_page (mm_page),
.tw_io_bit (tw_io_bit),
.issue_req_early (mm_issue_req_early),
.lvl_probe_hld (lvl_probe_hld),
.mm_misc2cf (mm_misc2cf),
.io_s_bit (io_s_bit),
.tw_rewrite_cam (tw_rewrite_cam),
.mm_misc2cf_2nd (mm_misc2cf_2nd),
// .mm_cpcyc_stb_l (mm_cpcyc_stb_l),
// .mm_cpsb_wrt (mm_cpsb_wrt),
.mem_issue_req (mm_issue_req),
.mem_issue_req2 (mm_issue_req2),
.mm_fb_req (mm_fb_req),
.mm_fb_size (mm_fb_size),
.mm_lvl15_int_l (mm_lvl15_int_l),
// .mm_sb_err (mm_sb_pe),
// .mm_iodaten (mm_iodaten),
// .mm_iostben (mm_iostben),
.mm_mreq (mm_mreq),
.m_in (msm_tlb_mbit),
.ptp_in (ptp_in),
.va_s_in (va_s_in),
.tw_sin (tw_sin),
// .sbc_pa_valid (mm_pa_valid),
// .mm_slock (mm_slock),
.asi_dcd6 (asi_dcd6),
.tlb_flush (tlb_flush),
.tlb_ram_lvl (tlb_ram_lvl),
.tlb_cam_lvl (tlb_cam_lvl),
.tw_tlb_vbit (tw_tlb_vbit),
// .mm_sbsize (mm_sbsize),
.mm_oddpar (mm_oddpar),
.mm_parity_en (mm_parity_en),
.mm_rfr_cntl (mm_rfr_cntl),
.tlb_asel (tlb_asel),
.mm_mfdaten (mm_mdata_en0),
/** dp outputs **/
.mm_fbpage_en (mm_fbpage_en), /* page hit en for afx*/
.sfar_write (sfar_write), /* SFAR input mux select*/
.sfar_read (sfar_read), /* SFAR input reset term*/
.tlb_acc_cmp (tlb_acc_cmp), /* TLB Acc bits for compares */
.tlb_mbit_cmp (tlb_mbit_cmp), /* TLB Mbit for compares */
.mbit_sel (mbit_sel), /* mux select fo mbit muxes.*/
.va_mux0_sel (va_mux0_sel), /* mux select fo VA muxes.*/
.va_mux1_sel (va_mux1_sel), /* mux select fo VA muxes.*/
.va_mux_sel (va_mux_sel), /* mux select fo VA muxes.*/
.hld_cxr (hld_cxr), /* Hold enable for CXR*/
.hold_sfar (hld_sfar), /* Hold enable for SFAR*/
.sel_mdat_mux (sel_mdat_mux), /* reg'd mdat mux sel. w/ asi_dcd*/
.hld_ctpr (hld_ctpr), /* load enable for CTPR*/
.hld_ibar (hld_ibar), /* load enable for IBAR*/
.hold_par (hold_par), /* load enable for PAR*/
.hld_afar (hld_afar), /* load enable for AFAR*/
.hld_mfar (hld_mfar), /* load enable for MFAR*/
.afar_write (afar_write), /* input mux select for AFAR.*/
.mfar_write (mfar_write), /* input mux select for MFAR.*/
.bp_sel_30 (bp_sel_30), /* Bypass mux selects for bits [30:29].*/
.bp_sel_28 (bp_sel_28), /* Bypass mux selects for bit [28].*/
.bp_sel_21 (bp_sel_21), /* Bypass mux selects for bits [27:21].*/
.bp_sel_20 (bp_sel_20), /* Bypass mux selects for bit [20].*/
.bp_sel_19 (bp_sel_19), /* Bypass mux selects for bit [19].*/
.bp_sel_18 (bp_sel_18), /* Bypass mux selects for bit [18].*/
.bp_sel_17 (bp_sel_17), /* Bypass mux selects for bit [17].*/
.bp_sel_16 (bp_sel_16), /* Bypass mux selects for bit [16].*/
.bp_sel_15 (bp_sel_15), /* Bypass mux selects for bit [15].*/
.bp_sel_14 (bp_sel_14), /* Bypass mux selects for bit [14].*/
.bp_mux_sel0 (bp_mux_sel0), /* Bypass mux select for D0 input */
.sr_tw (cpu_walk), /* Bypass mux select for cpu_walk */
.io_tlb_tw (io_walk), /* Bypass mux select for io_walk */
.dpa_sel_b (dpa_sel_b), /* DPA mux select for ROOT/level-1 PTE*/
.dpa_sel_8d (dpa_sel_8d), /* DPA mux select for bit [09:08] */
.ctpr_sel (ctpr_sel), /* DPA mux selects for bits [07:04].*/
.dpa_sel_0 (dpa_sel_0), /* DPA mux selects for bits [01:00].*/
.va_ptp8_sel (va_ptp8_sel),
.va_ptp4_sel (va_ptp4_sel),
.dp_mux1_sel (dp_mux1_sel), /* mux select for dp_mux1 read mux*/
.pamux_rd_sel (pamux_rd_sel), /* mux select for PA regs read mux*/
.boot_out_30 (boot_out_30), /* PA[30] for IO bypass path */
.tlb_wrt_tag (tlb_wrt_tag), /* write enable for TLB tag */
.misc (misc),
.precharge_early_0 (precharge_early_0),
.precharge_early_1 (precharge_early_1),
.mm_dacc_err (mm_dacc_err),
.mm_dacc_miss (mm_dacc_miss),
.mm_dacc_wp (mm_dacc_wp),
.mm_dacc_exc (mm_dacc_exc),
.mm_bp_dtct (mm_bp_dtct),
.mm_istat_avail (mm_istat_avail),
.mm_dstat_avail (mm_dstat_avail),
.mm_wbstb (mm_wbstb),
.mm_wbsel1 (mm_wbsel1),
.mm_icache_enbl (mm_icache_enbl),
.mm_dcache_enbl (mm_dcache_enbl),
.mm_cache_stat (mm_cache_stat),
.tlb_addr (tlb_addr),
.tlb_io_bit (tlb_io_bit),
// .mm_sbae (mm_sbae),
.mm_sbae_0 (mm_sbae_0),
.mm_rom_module_speed (mm_rom_module_speed),
// .mm_sscr_ba8 (mm_sscr_ba8),
.cam_reg_hld (cam_reg_hld),
.ram_reg_hld (ram_reg_hld),
.mm_fs_lvl (mm_fs_lvl),
.mm_fs_perr (mm_fs_perr),
.mm_fs_iae (mm_fs_iae),
.mm_fs_xerr (mm_fs_xerr),
.mm_fs_mmiss (mm_fs_mmiss),
.mm_fs_sbe (mm_fs_sbe),
.mm_fs_sto (mm_fs_sto),
.mm_fs_sptct (mm_fs_sptct),
.ld_pcntr_a (ld_pcntr_a),
.ld_pcntr_b (ld_pcntr_b),
.trig_a (trig_a),
.trig_b (trig_b),
.iva_wp_sel (iva_wp_sel),
.sel_brkpt_mux (sel_brkpt_mux),
.vaf_en_hld (vaf_en_hld),
.va_bp_hld (va_bp_hld),
.va_src_sel (va_src_sel),
.mm_mem_dbg (mm_mem_dbg),
.pcic_ifetch (pcic_ifetch),
.mm_go_standby (mm_go_standby), // automatic programmable standby
/*** Inputs ***/
.turn_off_standby (turn_off_standby), // turn off automatic programmable standby
.bm_sel (bm_sel), // if set, boot from SBus, else AFX
.w_sp_sel (w_sp_sel), // Speed select (for mmu status)
.w_div_ctl (w_div_ctl), // Divide by cntl (mmu status)
.mc_afx_to (mc_afx_to),
.ic_idle (ic_idle),
.tb_error (tb_error),
.m_miss (m_miss),
.misc_in (misc_in),
.mm_pa (mm_sb_pa),
.ld_op_e (ld_op_e),
.st_op_e (st_op_e),
.fpu_mem_e (fpu_mem_e),
.fp_trap_fix (fp_trap_fix),
.wb_3_size (wb_3_size),
.wb_3_asi (wb_3_asi),
.invalid_wb_entry (invalid_wb_entry),
.iu_size_e (iu_size_e),
.iu_asi_e (iu_asi_e),
.mc_mstb_l (mc_mstb_l),
.mc_mbsy (mc_mbsy),
// .sb_ioreq (sb_ioreq),
// .sb_ioreq_vld (sb_ioreq_vld),
.tlb_miss_raw (tlb_miss_raw),
.acc_ok (acc_ok),
.iu_pipe_hold (iu_pipe_hold),
.tlb_acc_raw (tb_out[2:0]),
.tlb_c_bit (tb_out[5]),
.iu_in_trap (iu_in_trap),
.io_space (io_space),
.cntl_space (cntl_space),
.fb_space (fb_space),
.mem_space (mem_space),
.pci_space (pci_space),
// .sb_cyc_pnd (sb_cyc_pnd),
.cxr (cxr),
.r_d_vaddr (r_d_vaddr_out),
// .sb_err_type (sb_err_type),
// .sb_wrt_err (sb_write_error),
// .sb_errsize (sb_errsize),
.tlb_lvl (tb_out[27:25]),
.pa_mux_rd (pa_mux_rd),
.dp_perr (dp_perr),
// .sb_sbslot (sb_sbslot),
.brk_pt_hit (brk_pt_hit),
.odd_wd (odd_wd),
// .sb_ioa (sb_ioa[31:24]),
// .sb_va_val_l (sb_va_val_l),
.ss_clock (ss_clock),
.ss_reset (ss_reset),
.ss_reset_any (ss_reset_any),
.ss_scan_mode (ss_scan_mode),
.ss_scan_in (dp_mmu_scan_out),
.mm_hold_rst (mm_hold_rst),
.mm_dabort (mm_dabort),
.mm_dccfstb (mm_dcstben), /*** NOW for Cache Fill bus - not misc */
.mm_dcdaten (mm_dcdaten_in),
.mm_icdaten (mm_icdaten),
.mm_dct_daten (mm_dct_daten),
.mm_iccfstb (mm_icstben), /* I-cache data strobe (cache fill bus) */
.mm_iabort (mm_iabort),
.tlb_co_in (tlb_co_in),
.tlb_c_rd (tlb_c_rd),
.mm_icstben (icstben_asi), /* I-cache ASI write strobe (misc bus) */
.ss_scan_out (m_mmu_cache_scan_out),
.par_sel (par_sel),
.hld_dpar (hld_dpar),
.hld_ipar (hld_ipar),
.ic_miss_or_part (ic_miss_or_part),
.ic_miss_and_part (ic_miss_and_part),
.dc_miss_or_part (dc_miss_or_part),
.dc_miss_and_part (dc_miss_and_part),
.dc_miss_sustain (dc_miss_sustain),
.dt_hit_w (dt_hit_w),
.it_hit_f (it_hit_f), // itag hit in f stage ** ASSERTED LOW **
.ic_miss_sustain (ic_miss_sustain),
.wb_valid (wb_valid),
.iu_sfs_sup (iu_sfs_sup),
.iu_sfs_perr (iu_sfs_perr),
.iu_sfs_xerr (iu_sfs_xerr),
.iu_sfs_mmiss (iu_sfs_mmiss),
.iu_sfs_iae (iu_sfs_iae),
.iu_sfs_sbe (iu_sfs_sbe),
.iu_sfs_sto (iu_sfs_sto),
.iu_sfs_prtct (iu_sfs_prtct),
.iu_sfs_priv (iu_sfs_priv),
.iu_sfs_lvl (iu_sfs_lvl),
.iu_mm_iacc_wp_exc_d (iu_mm_iacc_wp_exc_d),
.dcc_idle (dcc_idle),
.ihold_d1 (ihold_d1),
.dhold_d1 (dhold_d1),
.dc_shold (dc_shold),
.did_fetch (did_fetch),
.hold_fetch_f_l (hold_fetch_f_l),
.fhold_d1 (fhold_d1),
.fhold_fqfull_d1 (fhold_fqfull_d1),
.iu_sup_mode (iu_sup_mode),
.pcntr_a_co (pcntr_a_co),
.pcntr_b_co (pcntr_b_co),
.p_reply_dec (p_reply_dec),
.page_hit (page_hit),
.page_miss0 (page_miss0),
.page_miss1 (page_miss1)
);
dp_mmu MMU_dp(
.mc_refresh (mc_refresh),
.tw_io_bit (tw_io_bit),
.io_s_bit (io_s_bit),
.bm_sel (bm_sel),
.falcon_exists (1'b1),
.lvl_probe_hld (lvl_probe_hld),
.pcntr_a_co (pcntr_a_co),
.pcntr_b_co (pcntr_b_co),
.page_hit (page_hit),
.page_miss0 (page_miss0),
.page_miss1 (page_miss1),
.mm_fb_page (mm_fb_page),
.mm_fbpage_en (mm_fbpage_en),
.va_tag_out (tlb_tag_in),
.cxr (cxr),
.r_d_vaddr_out (r_d_vaddr_out),
.pa_out (mm_pa),
.mm_sb_pa (mm_sb_pa),
.mm_caddr (mm_caddr),
.pa_mux_rd (pa_mux_rd),
.io_space (io_space),
.cntl_space (cntl_space),
.fb_space (fb_space),
.mem_space (mem_space),
.pci_space (pci_space),
.wb_3_size (wb_3_size),
.wb_3_asi (wb_3_asi),
.brk_pt_hit (brk_pt_hit),
.odd_wd (odd_wd),
.io_addr ({1'b1, 1'b1, 1'b1, 1'b1,
1'b1, 1'b1, 1'b1, 1'b1,
1'b1, 1'b1, 1'b1, 1'b1,
1'b1, 1'b1, 1'b1, 1'b1,
1'b1, 1'b1, 1'b1, 1'b1,
1'b1, 1'b1, 1'b1, 1'b1,
1'b1, 1'b1, 1'b1, 1'b1,
1'b1, 1'b1, 1'b1, 1'b1}),
.i_vaddr (iu_iva_g),
.d_vaddr (iu_dva_e),
.tlb_data_in (tlb_data_in),
.misc_bus_in (misc_in),
.mmu_ptp_in (ptp_in),
.iva_s_in (va_s_in),
.dva_s_in (va_s_in),
.msm_mbit_in (msm_tlb_mbit),
.sfar_write (sfar_write),
.sfar_read (sfar_read),
.asi_dcd6 (asi_dcd6),
.tlb_acc_cmp (tlb_acc_cmp),
.tlb_mbit_cmp (tlb_mbit_cmp),
.mbit_sel (mbit_sel),
.va_mux0_sel (va_mux0_sel),
.va_mux1_sel (va_mux1_sel),
.va_mux_sel (va_mux_sel),
.mm_page_hit_en (mm_page_hit_en),
.mm_issue_req (mm_issue_req),
.mm_fb_req (mm_fb_req),
.hld_cxr (hld_cxr),
.hld_sfar (hld_sfar),
.tlb_ram_lvl (tlb_ram_lvl),
.tlb_cam_lvl (tlb_cam_lvl),
.sel_mdat_mux (sel_mdat_mux),
.tb_out (tb_out),
.hld_ctpr (hld_ctpr),
.hld_ibar (hld_ibar),
.hold_par (hold_par),
.hld_afar (hld_afar),
.hld_mfar (hld_mfar),
.afar_write (afar_write),
.mfar_write (mfar_write),
.bp_sel_30 (bp_sel_30),
.bp_sel_28 (bp_sel_28),
.bp_sel_21 (bp_sel_21),
.bp_sel_20 (bp_sel_20),
.bp_sel_19 (bp_sel_19),
.bp_sel_18 (bp_sel_18),
.bp_sel_17 (bp_sel_17),
.bp_sel_16 (bp_sel_16),
.bp_sel_15 (bp_sel_15),
.bp_sel_14 (bp_sel_14),
.bp_mux_sel0 (bp_mux_sel0),
.cpu_walk (cpu_walk),
.io_walk (io_walk),
.dpa_sel_b (dpa_sel_b),
.dpa_sel_8d (dpa_sel_8d), /* DPA mux select for bit [09:08] */
.ctpr_sel (ctpr_sel),
.dpa_sel_0 (dpa_sel_0),
.va_ptp8_sel (va_ptp8_sel),
.va_ptp4_sel (va_ptp4_sel),
.dp_mux1_sel (dp_mux1_sel),
.pamux_rd_sel (pamux_rd_sel),
.tlb_rd_tag (tlb_tag_out),
.boot_out_30 (boot_out_30),
.io_tlb_nxt (tlb_io_bit),
.tlb_wrt_tag (tw_sin),
.tlb_s_bit (tlb_flush),
.tw_tlb_vbit (tw_tlb_vbit),
.dp_mmu_scan_in (mc_tlb_scan_out),
.dp_mmu_scan_out (dp_mmu_scan_out),
.par_sel (par_sel),
.hld_dpar (hld_dpar),
.hld_ipar (hld_ipar),
.cam_reg_hld (cam_reg_hld),
.ram_reg_hld (ram_reg_hld),
.iu_size_e (iu_size_e),
.iu_asi_e (iu_asi_e[1:0]),
.precharge_early_0 (precharge_early_0),
.precharge_early_1 (precharge_early_1),
.mc_mbsy (mc_mbsy),
.mc_caddr_hld (mc_caddr_hld),
.pipe_hold4mmu_dp (pipe_hold4mmu_dp),
.wb0_hold_lo (wb0_hold_lo),
.wb1_hold_lo (wb1_hold_lo),
.wb2_hold_lo (wb2_hold_lo),
.wb3_hold_lo (wb3_hold_lo),
.wb_1_sel (wb_1_sel),
.wb_2_sel (wb_2_sel),
.wb_3_sel (wb_3_sel),
.ic_miss (ic_miss),
.mem_idle (mem_idle),
.afx_rst_page_vld (afx_rst_page_vld),
.ld_pcntr_a (ld_pcntr_a),
.ld_pcntr_b (ld_pcntr_b),
.trig_a (trig_a),
.trig_b (trig_b),
.iva_wp_sel (iva_wp_sel),
.sel_brkpt_mux (sel_brkpt_mux),
.vaf_en_hld (vaf_en_hld),
.va_bp_hld (va_bp_hld),
.va_src_sel (va_src_sel),
.tw_rewrite_cam (tw_rewrite_cam),
.ss_clock (ss_clock),
.ss_reset (ss_reset),
.ss_scan_mode (ss_scan_mode)
);
S_TLB MMU_tlb(
.RD_OUT27 ( tb_out[27] ),
.RD_OUT26 ( tb_out[26] ),
.RD_OUT25 ( tb_out[25] ),
.RD_OUT24 ( tb_out[24] ),
.RD_OUT23 ( tb_out[23] ),
.RD_OUT22 ( tb_out[22] ),
.RD_OUT21 ( tb_out[21] ),
.RD_OUT20 ( tb_out[20] ),
.RD_OUT19 ( tb_out[19] ),
.RD_OUT18 ( tb_out[18] ),
.RD_OUT17 ( tb_out[17] ),
.RD_OUT16 ( tb_out[16] ),
.RD_OUT15 ( tb_out[15] ),
.RD_OUT14 ( tb_out[14] ),
.RD_OUT13 ( tb_out[13] ),
.RD_OUT12 ( tb_out[12] ),
.RD_OUT11 ( tb_out[11] ),
.RD_OUT10 ( tb_out[10] ),
.RD_OUT9 ( tb_out[9] ),
.RD_OUT8 ( tb_out[8] ),
.RD_OUT7 ( tb_out[7] ),
.RD_OUT6 ( tb_out[6] ),
.RD_OUT5 ( tb_out[5] ),
.RD_OUT4 ( tb_out[4] ),
.RD_OUT3 ( tb_out[3] ),
.RD_OUT2 ( tb_out[2] ),
.RD_OUT1 ( tb_out[1] ),
.RD_OUT0 ( tb_out[0] ),
.CD_OUT41 ( cd_out[41] ),
.CD_OUT40 ( cd_out[40] ),
.CD_OUT39 ( cd_out[39] ),
.CD_OUT38 ( cd_out[38] ),
.CD_OUT37 ( cd_out[37] ),
.CD_OUT36 ( cd_out[36] ),
.CD_OUT35 ( cd_out[35] ),
.CD_OUT34 ( cd_out[34] ),
.CD_OUT33 ( cd_out[33] ),
.CD_OUT32 ( cd_out[32] ),
.CD_OUT31 ( cd_out[31] ),
.CD_OUT30 ( cd_out[30] ),
.CD_OUT29 ( cd_out[29] ),
.CD_OUT28 ( cd_out[28] ),
.CD_OUT27 ( cd_out[27] ),
.CD_OUT26 ( cd_out[26] ),
.CD_OUT25 ( cd_out[25] ),
.CD_OUT24 ( cd_out[24] ),
.CD_OUT23 ( cd_out[23] ),
.CD_OUT22 ( cd_out[22] ),
.CD_OUT21 ( cd_out[21] ),
.CD_OUT20 ( cd_out[20] ),
.CD_OUT19 ( cd_out[19] ),
.CD_OUT18 ( cd_out[18] ),
.CD_OUT17 ( cd_out[17] ),
.CD_OUT16 ( cd_out[16] ),
.CD_OUT15 ( cd_out[15] ),
.CD_OUT14 ( cd_out[14] ),
.CD_OUT13 ( cd_out[13] ),
.CD_OUT12 ( cd_out[12] ),
.CD_OUT11 ( cd_out[11] ),
.CD_OUT10 ( cd_out[10] ),
.CD_OUT9 ( cd_out[9] ),
.CD_OUT8 ( cd_out[8] ),
.CD_OUT7 ( cd_out[7] ),
.CD_OUT6 ( cd_out[6] ),
.CD_OUT5 ( cd_out[5] ),
.CD_OUT4 ( cd_out[4] ),
.CD_OUT3 ( cd_out[3] ),
.CD_OUT2 ( cd_out[2] ),
.CD_OUT1 ( cd_out[1] ),
.CD_OUT0 ( cd_out[0] ),
.MISS ( tlb_miss_raw ),
.ACC_OK ( acc_ok ),
.ERROR ( tb_error ),
.M_MISS ( m_miss ),
.RD_IN27 ( tlb_data_in[27] ),
.RD_IN26 ( tlb_data_in[26] ),
.RD_IN25 ( tlb_data_in[25] ),
.RD_IN24 ( tlb_data_in[24] ),
.RD_IN23 ( tlb_data_in[23] ),
.RD_IN22 ( tlb_data_in[22] ),
.RD_IN21 ( tlb_data_in[21] ),
.RD_IN20 ( tlb_data_in[20] ),
.RD_IN19 ( tlb_data_in[19] ),
.RD_IN18 ( tlb_data_in[18] ),
.RD_IN17 ( tlb_data_in[17] ),
.RD_IN16 ( tlb_data_in[16] ),
.RD_IN15 ( tlb_data_in[15] ),
.RD_IN14 ( tlb_data_in[14] ),
.RD_IN13 ( tlb_data_in[13] ),
.RD_IN12 ( tlb_data_in[12] ),
.RD_IN11 ( tlb_data_in[11] ),
.RD_IN10 ( tlb_data_in[10] ),
.RD_IN9 ( tlb_data_in[9] ),
.RD_IN8 ( tlb_data_in[8] ),
.RD_IN7 ( tlb_data_in[7] ),
.RD_IN6 ( tlb_data_in[6] ),
.RD_IN5 ( tlb_data_in[5] ),
.RD_IN4 ( tlb_data_in[4] ),
.RD_IN3 ( tlb_data_in[3] ),
.RD_IN2 ( tlb_data_in[2] ),
.RD_IN1 ( tlb_data_in[1] ),
.RD_IN0 ( tlb_data_in[0] ),
.CD_IN41 ( tlb_tag_in[41] ),
.CD_IN40 ( tlb_tag_in[40] ),
.CD_IN39 ( tlb_tag_in[39] ),
.CD_IN38 ( tlb_tag_in[38] ),
.CD_IN37 ( tlb_tag_in[37] ),
.CD_IN36 ( tlb_tag_in[36] ),
.CD_IN35 ( tlb_tag_in[35] ),
.CD_IN34 ( tlb_tag_in[34] ),
.CD_IN33 ( tlb_tag_in[33] ),
.CD_IN32 ( tlb_tag_in[32] ),
.CD_IN31 ( tlb_tag_in[31] ),
.CD_IN30 ( tlb_tag_in[30] ),
.CD_IN29 ( tlb_tag_in[29] ),
.CD_IN28 ( tlb_tag_in[28] ),
.CD_IN27 ( tlb_tag_in[27] ),
.CD_IN26 ( tlb_tag_in[26] ),
.CD_IN25 ( tlb_tag_in[25] ),
.CD_IN24 ( tlb_tag_in[24] ),
.CD_IN23 ( tlb_tag_in[23] ),
.CD_IN22 ( tlb_tag_in[22] ),
.CD_IN21 ( tlb_tag_in[21] ),
.CD_IN20 ( tlb_tag_in[20] ),
.CD_IN19 ( tlb_tag_in[19] ),
.CD_IN18 ( tlb_tag_in[18] ),
.CD_IN17 ( tlb_tag_in[17] ),
.CD_IN16 ( tlb_tag_in[16] ),
.CD_IN15 ( tlb_tag_in[15] ),
.CD_IN14 ( tlb_tag_in[14] ),
.CD_IN13 ( tlb_tag_in[13] ),
.CD_IN12 ( tlb_tag_in[12] ),
.CD_IN11 ( tlb_tag_in[11] ),
.CD_IN10 ( tlb_tag_in[10] ),
.CD_IN9 ( tlb_tag_in[9] ),
.CD_IN8 ( tlb_tag_in[8] ),
.CD_IN7 ( tlb_tag_in[7] ),
.CD_IN6 ( tlb_tag_in[6] ),
.CD_IN5 ( tlb_tag_in[5] ),
.CD_IN4 ( tlb_tag_in[4] ),
.CD_IN3 ( tlb_tag_in[3] ),
.CD_IN2 ( tlb_tag_in[2] ),
.CD_IN1 ( tlb_tag_in[1] ),
.CD_IN0 ( tlb_tag_in[0] ),
.FLUSH ( tlb_flush ),
.TLB_WE ( tlb_wrt_tag ),
.ASEL ( tlb_asel ),
.ADDR4 ( tlb_addr[4] ),
.ADDR3 ( tlb_addr[3] ),
.ADDR2 ( tlb_addr[2] ),
.ADDR1 ( tlb_addr[1] ),
.ADDR0 ( tlb_addr[0] ),
| This page: |
Created: | Thu Aug 19 11:59:17 1999 |
| From: |
../../../sparc_v8/ssparc/mmu/rtl/mmu.v
|