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//  @(#)multiplierslice.v	1.1  4/7/92
//

module MultiplierSlice (Phi,
// ctl inputs
                        InitialMulStep,
/* 		notInitialSumZero, */
                        InitialCarryBit,
                        SumCarryLoadEn,
                        Shift,
                        Pos,
                        Zero,
                        SumOut0,
                        CarryOut0,
                        CarryOut3,
// inputs
                        Breg,
// ctl outputs
                        SumIn[2:0],
                        CarryIn[2:0],
                        SALSBs, SBLSBs, SCLSBs,
                        CALSB,  CBLSB,  CCLSB,
// outputs
                        SD[`FracMSB-1:1], // SumForAreg
                        CD[`FracMSB-1:2] );
input  Phi;
input
/* 	notInitialSumZero, */
       InitialMulStep,
       InitialCarryBit,
       SumCarryLoadEn;
input [3:0]     Shift,
                Pos,
                Zero;
input  SumOut0,
       CarryOut0,
       CarryOut3;
input  [`FracMSB:1] Breg;
output [`FracMSB:0] SumIn, CarryIn;
output [1:0] SALSBs, SBLSBs, SCLSBs;
output       CALSB,  CBLSB,  CCLSB;
output [`FracMSB:1] SD;
output [`FracMSB:2] CD;

CSRegSlice csr       (Phi,
                      InitialMulStep,
/* 		notInitialSumZero, */
                      InitialCarryBit,
                      SumCarryLoadEn,
                      {SD[`FracMSB:1], SumOut0},
                      {CD[`FracMSB:2], CarryOut3, CarryOut0},
                      Breg [`FracMSB:1],
                      SumIn[`FracMSB:0],
                      CarryIn[`FracMSB:0]);
CSArray csa   ( Shift,
                Pos,
                Zero,
                SumIn[`FracMSB:3],
                CarryIn[`FracMSB:3],
                Breg [`FracMSB:1],
                SALSBs, SBLSBs, SCLSBs,
                CALSB,  CBLSB,  CCLSB,
                SD[`FracMSB:1],
                CD[`FracMSB:2]);
endmodule