HierarchyFilesModulesSignalsTasksFunctionsHelp
Prev12
   .bus_idle			( bus_idle		)

   );

// Added spare cells 

        spares  pcic_spares ();

endmodule
12
HierarchyFilesModulesSignalsTasksFunctionsHelp

This page: Created:Thu Aug 19 12:02:58 1999
From: ../../../sparc_v8/ssparc/pcic/rtl/pcic.v

Verilog converted to html by v2html 5.0 (written by Costas Calamvokis).Help