/******************************************************************************/
/* */
/* Copyright (c) 1999 Sun Microsystems, Inc. All rights reserved. */
/* */
/* The contents of this file are subject to the current version of the Sun */
/* Community Source License, microSPARCII ("the License"). You may not use */
/* this file except in compliance with the License. You may obtain a copy */
/* of the License by searching for "Sun Community Source License" on the */
/* World Wide Web at http://www.sun.com. See the License for the rights, */
/* obligations, and limitations governing use of the contents of this file. */
/* */
/* Sun Microsystems, Inc. has intellectual property rights relating to the */
/* technology embodied in these files. In particular, and without limitation, */
/* these intellectual property rights may include one or more U.S. patents, */
/* foreign patents, or pending applications. */
/* */
/* Sun, Sun Microsystems, the Sun logo, all Sun-based trademarks and logos, */
/* Solaris, Java and all Java-based trademarks and logos are trademarks or */
/* registered trademarks of Sun Microsystems, Inc. in the United States and */
/* other countries. microSPARC is a trademark or registered trademark of */
/* SPARC International, Inc. All SPARC trademarks are used under license and */
/* are trademarks or registered trademarks of SPARC International, Inc. in */
/* the United States and other countries. Products bearing SPARC trademarks */
/* are based upon an architecture developed by Sun Microsystems, Inc. */
/* */
/******************************************************************************/
`timescale 1ns/100ps
/***************************************************************************
*** pcic.v
***
*** Description:
*** This is the pci controller for the microsparc IIEP.
***
****************************************************************************
****************************************************************************/
![[Up: ssparc_core ssparc_pcic]](v2html-up.gif)
module pcic
(
pcic_scan_in,
pcic_scan_out,
little_endian,
// Misc unidrectional
ext_req_l,
ext_int_,
ext_int_oe,
ext_gnt_l,
falcon_int,
// AFX Drive enables
pcic_ab_oen,
pcic_db_oen,
pcic_afxm_db_oen,
// falcon drive to IO
ab_out,
db_out1,
db_out2,
mpar_out1,
mpar_out2,
// falcon unidirectional
am_cstb_l,
am_read,
am_wm,
aen,
write_l,
lo_addr,
valid_l,
cas_cyc,
am_gnt_l,
mm_oddpar,
dp_perr,
tmr_clk, // timer div by 4 clock
gclk,
s_reply,
p_reply,
db,
ab,
mpar,
reset,
// pci Drive enables
top_ADEnable,
bot_ADEnable,
right_ADEnable,
cbeEnable,
PAREnable,
frameEn,
trdyEn,
irdyEn,
stopEn,
devselEn,
perrEn,
serrEnable,
// pci from the core to io pad
AD_out,
CBEnnout,
PAR_out,
mas_framen_out,
tar_trdyout,
mas_irdyn_out,
tar_stopout,
tar_devselout,
mas_req_out,
serro_,
perro_,
// pci Drive from io_pad to core
ad_bus_i,
cben_bus_i,
par_i,
_frame_i,
_frame_ia,
_frame_ib,
_irdy_i,
_irdy_ia,
_irdy_ib,
_irdy_ic,
_perr_i,
_serr_i,
_trdy_i,
_trdy_ia,
_trdy_ib,
_stop_i,
_devsel_i,
PCI_rstn_in,
pci_clk,
rstnn,
// scan inputs / output
csl_scan_mode,
pci_clk_sync,
pci_clk_sync_,
gclk_sync,
gclk_sync_,
pci_clk_,
boot_mode,
mm_go_standby,
pin_go_standby,
turn_off_standby,
go_standby,
standby_dsbl_tlb,
pcic_idle,
mm_lvl15_int_l,
any_intrnl_int_l,
bm_sel,
input_reset_l,
iu_error,
pci_slave_mode,
raw_pci_rst_l,
sw_rst,
en_sw_rst_nonwd,
en_pci_sw_rst
);
input input_reset_l;
input iu_error;
input pci_slave_mode;
input raw_pci_rst_l;
output sw_rst;
output en_sw_rst_nonwd;
output en_pci_sw_rst;
input pcic_scan_in;
output pcic_scan_out;
input little_endian; // processor little_endian mode
input [3:0] ext_req_l;
input [7:0] ext_int_;
output [7:0] ext_int_oe;
output [3:0] ext_gnt_l;
output [3:0] falcon_int;
wire [3:0] ext_gnt_l;
wire [3:0] falcon_int;
output pcic_ab_oen;
wire pcic_ab_oen;
output pcic_db_oen;
output pcic_afxm_db_oen;
wire pcic_db_oen;
output [14:0] ab_out;
output [63:0] db_out1;
output [63:0] db_out2;
wire [14:0] ab_out;
wire [63:0] db_out1;
wire [63:0] db_out2;
output [1:0] mpar_out1;
output [1:0] mpar_out2;
wire [1:0] mpar_out1;
wire [1:0] mpar_out2;
output am_cstb_l;
output am_read;
output [1:0] am_wm;
wire [1:0] am_wm;
input aen;
input write_l;
input lo_addr;
input valid_l;
input cas_cyc;
input am_gnt_l;
input mm_oddpar;
input [1:0] dp_perr;
input tmr_clk;
input gclk;
input pci_clk;
output rstnn;
wire rstnn;
input [1:0] s_reply;
output [1:0] p_reply;
wire [1:0] p_reply;
input [63:0] db;
input [14:0] ab;
input [1:0] mpar;
input reset;
output top_ADEnable;
output bot_ADEnable;
output right_ADEnable;
output cbeEnable;
output PAREnable;
output frameEn;
output trdyEn;
output irdyEn;
output stopEn;
output devselEn;
output perrEn;
output serrEnable;
output [31:0] AD_out;
output [3:0] CBEnnout;
output PAR_out;
output mas_framen_out;
output tar_trdyout;
output mas_irdyn_out;
output tar_stopout;
output tar_devselout;
output mas_req_out;
output serro_;
output perro_;
input [31:0] ad_bus_i;
input [ 3:0] cben_bus_i;
input par_i;
input _frame_i;
input _frame_ia;
input _frame_ib;
input _irdy_i;
input _irdy_ia;
input _irdy_ib;
input _irdy_ic;
input _perr_i;
input _serr_i;
input _trdy_i;
input _trdy_ia;
input _trdy_ib;
input _stop_i;
input _devsel_i;
input PCI_rstn_in;
input csl_scan_mode;
input pci_clk_sync;
input pci_clk_sync_;
input gclk_sync;
input gclk_sync_;
input pci_clk_;
input boot_mode; // boot mode on instruction fetches
input [1:0] bm_sel; // boot mode sel != 00 is pci
input mm_go_standby; // programmable MID bit for standby
input pin_go_standby; // external pin for standby
input standby_dsbl_tlb; // standby power down mode to iotlb
input mm_lvl15_int_l; // internal level 15 interrupt
output any_intrnl_int_l; // any level 15 output to external pin
output go_standby; // external pin for standby
output turn_off_standby; // reset to MID standby, for external activity
output pcic_idle; // output to signal idle, go to power down mode
// wires for pci config access
wire [31:0] config_data_in;
wire [7:0] config_add;
wire [3:0] config_wbe;
wire host_config_access_busy;
wire pci_config_access_busy;
wire config_write;
wire go_standby;
wire pcic_idle;
wire sm_idle;
wire turn_off_standby;
// add following declarations from Ravicad's system.v:
wire [31:0] cdec_address ;
wire [3:0] cdec_curCmd ;
wire cdec_write_op ;
wire [31:0] pci_config_wdata ;
wire [7:0] pci_config_wadd ;
wire [7:0] pci_config_radd ;
wire pci_config_we ;
wire [31:0] pci_config_rdata ;
wire [31:0] cfg_config_out ;
wire afx_rd_wrt ;
wire [31:0] mas_rcv1_dataout ;
wire [ 3:0] mas_rcv1_be_out ;
wire [ 3:0] tar_rcv1_fifo_next_be_out;
wire [ 3:0] tar_rcv2_fifo_next_be_out;
wire [31:0] mas_rcv2_dataout ;
wire [ 3:0] mas_rcv2_be_out ;
wire mrcv1_fifo_read, mrcv2_fifo_read;
//wire [31:0] mxmit2_data_in ;
wire [ 3:0] mxmit2_data_be_in ;
//wire [31:0] mxmit1_data_in ;
wire [ 3:0] mxmit1_data_be_in ;
wire [63:0] pci_data_out;
wire req1 ;
wire mas_start_dma ;
wire host1_complete ;
wire host1_perr ;
wire host1_async_perr ;
wire [3:0] cmd_out ;
wire [31:0] address1 ;
wire [7:0] wcount1 ;
wire force_pci_abort ;
wire force_pci_disconnect;
wire io_read_ready ;
wire io_write_ready ;
wire retry_condition ;
wire tar_valid_cmd ;
wire tar_valid_cmd_early ;
wire [31:0] tar_rcv1_dataout ;
wire [31:0] tar_rcv2_dataout ;
wire [ 3:0] tar_rcv1_fifo_be_out ;
wire [ 3:0] tar_rcv2_fifo_be_out ;
wire [31:0] tar_xmit1_data_in ;
wire [ 3:0] tar_xmit1_data_be_in ;
wire [31:0] tar_xmit2_data_in ;
wire [ 3:0] tar_xmit2_data_be_in ;
wire [ 2:0] tar_xmit1_fifo_write_ptr ;
wire [ 2:0] tar_xmit2_fifo_write_ptr ;
// wires for the IO connections
wire DBEnable1, DBEnable2;
wire [31:0] AD_out;
wire [31:0] ad_bus_i;
wire [ 3:0] CBEnnout;
wire [ 3:0] cben_bus_i;
wire PAR_out;
wire par_i;
wire mas_framen_out;
wire mas_irdyn_out;
wire perro_;
wire _perr_i;
wire serro_;
wire _serr_i;
wire tar_devselout;
wire mas_req_out;
wire _devsel_i;
wire tar_trdyout;
wire tar_stopout;
wire _stop_i;
wire PCI_rstn_in;
// PCI drive enables
wire top_ADEnable;
wire bot_ADEnable;
wire right_ADEnable;
wire cbeEnable;
wire PAREnable;
wire frameEn;
wire trdyEn;
wire irdyEn;
wire stopEn;
wire devselEn;
wire perrEn;
wire serrEnable;
// end Ravicad declarations from Ravicad's system.v
// Wires for the afx connections
wire [3:0] smbar0;
wire [3:0] smbar1;
wire [3:0] sibar;
wire [3:0] msize0;
wire [3:0] msize1;
wire [7:0] pmbar0;
wire [7:0] pmbar1;
wire [7:0] pibar;
wire [3:0] isize;
wire burst_enable;
wire prefetch_enable;
wire arb_lvl_en;
wire arb_disable;
wire cfg_fast_decode;
wire [14:0] arb_asgn_reg;
wire [3:0] afx_master_cfg;
wire req_quiescence;
wire ack_quiescence;
wire req_q_retry;
wire [15:0] discard_timer; //only 15 bits actually used
wire new_frame;
wire bus_idle;
wire any_xint;
wire pci_master_idle;
wire afxm_idle_cyc;
wire afx_m_idle;
wire pci_slave_idle;
wire [63:0] afx_slave_read_data;
wire [1:0] afx_slave_read_data_parity;
wire afx_slave_drive_db;
wire [31:0] afx_mast_error_address;
wire [3:0] afx_mast_error_cmd;
wire afx_mast_error;
wire [31:0] iotlb_cd_in_reg;
wire [31:0] iotlb_rd_in_reg;
wire [31:0] iotlb_cd_out_reg;
wire [31:0] iotlb_rd_out_reg;
wire [7:0] iotlb_cntl_reg;
wire iotlb_cntl_wrt;
wire iotlb_err;
wire [31:0] iotlb_err_address;
wire iotlb_enable;
wire afx_master_drive_db;
wire afx_master_drive_ab;
wire [14:0] afx_master_address;
wire [3:0] pci_config_wbe_l; //used for io address generate
wire [3:0] pci_config_wbe; // used for configuration write byte enables
// resync and scan clock connections
wire pci_clk_sync;
wire pci_clk_sync_;
wire gclk_sync;
wire gclk_sync_;
wire pci_clk_;
wire reset_l_reg;
wire [1:0] reset_reg;
flops flops ( .gclk (gclk),
.pci_clk (pci_clk),
.pci_clk_ (pci_clk_), // added input port per request 5-16-97
.reset (reset),
.DBEnable1 (DBEnable1),
.DBEnable2 (DBEnable2),
.reset_l_reg (reset_l_reg),
.reset_reg (reset_reg),
.rstnn (rstnn),
.pcic_db_oen (pcic_db_oen),
.pcic_afxm_db_oen (pcic_afxm_db_oen)
);
f_afx_slave f_afx_slave(
.pcim_big_endian(pcim_big_endian),
.little_endian (little_endian ),
.boot_mode (boot_mode ),
.bm_sel (bm_sel ),
.pci_clk_sync (pci_clk_sync ),
.pci_clk_sync_ (pci_clk_sync_ ),
.gclk_sync (gclk_sync ),
.gclk_sync_ (gclk_sync_ ),
// this needs to be hooked up to a gclk early in the clock tree
.fast_gclk (gclk),
.clock (gclk),
.pci_clk (pci_clk),
.reset (reset_reg[1]),
// Configuration register signals
.smbar0 (smbar0),
.smbar1 (smbar1),
.sibar (sibar),
.msize0 (msize0),
.msize1 (msize1),
.pmbar0 (pmbar0),
.pmbar1 (pmbar1),
.pibar (pibar),
.isize (isize),
.burst_enable (burst_enable),
.prefetch_enable (prefetch_enable),
.pci_config_wdata (pci_config_wdata),
.pci_config_wbe_l (pci_config_wbe_l),
.pci_config_wbe (pci_config_wbe),
.pci_config_wadd (pci_config_wadd),
.pci_config_radd (pci_config_radd),
.pci_config_we (pci_config_we),
.pci_config_rdata (pci_config_rdata),
// add for pci configuration accesses
.config_wbe (config_wbe),
.config_add (config_add),
.config_data_in (config_data_in),
.host_config_access_busy (host_config_access_busy),
.pci_config_access_busy (pci_config_access_busy),
.config_write (config_write),
.afx_mast_error_address (afx_mast_error_address),
.afx_mast_error_cmd (afx_mast_error_cmd),
.afx_mast_error (afx_mast_error),
.sm_idle (sm_idle),
.select_falcon_data (afx_rd_wrt),
// AFX BUS signals
.aen (aen),
.ab (ab),
.db (db),
.s_reply (s_reply),
.write_l (write_l),
.lo_addr (lo_addr),
.p_reply (p_reply),
.afx_slave_read_data (db_out1),
.afx_slave_read_data_parity (mpar_out1),
.afx_slave_drive_db (DBEnable1),
// PCI core signals
.pci_req (req1),
.pci_complete (host1_complete),
.pci_error (host1_fatal),
.pci_perror (host1_perr),
.pci_async_perror (host1_async_perr),
.pci_address (address1),
.pci_wcount (wcount1),
.pci_command (cmd_out),
.pci_last (pci_last),
.pci_mast_fifo_write_lo (mxmit1_fifo_write),
.pci_mast_fifo_write_hi (mxmit2_fifo_write),
.pci_mast_xmit_fifo_flush (mas_xmt_fifo_flush),
.pci_mast_rcv_fifo_flush (mas_rcv_fifo_flush),
.pci_mast_rcv_fifo_empty_lo (mas_rcv1_fifo_empty),
.pci_mast_rcv_fifo_empty_hi (mas_rcv2_fifo_empty),
.pci_mast_rcv_fifo_read_lo (mrcv1_fifo_read),
.pci_mast_rcv_fifo_read_hi (mrcv2_fifo_read),
.pci_data_out (pci_data_out),
.pci_bm_out_lo_l (mxmit1_data_be_in),
.pci_bm_out_hi_l (mxmit2_data_be_in),
.mas_rcv1_dataout (mas_rcv1_dataout),
.mas_rcv2_dataout (mas_rcv2_dataout),
.mas_start_dma (mas_start_dma)
);
arbiter arbiter(
.reset (reset_reg[0]),
.clock (pci_clk),
.req_ (ext_req_l),
.req_host_ (mas_req_out),
.granto_ (ext_gnt_l),
.granto_host_ (grant_host_),
.new_frame (new_frame),
.bus_idle (bus_idle),
.req_conf_ (req_conf_),
.grant_conf_ (grant_conf_),
.arb_lvl_en (arb_lvl_en),
.arb_disable (arb_disable),
.arb_asgn_reg (arb_asgn_reg),
.req_quiescence (req_quiescence),
.mm_go_standby (mm_go_standby),
.pin_go_standby (pin_go_standby),
.turn_off_standby (turn_off_standby),
.go_standby (go_standby),
.pcic_idle (pcic_idle),
.any_xint (any_xint),
.sm_idle (sm_idle),
.mas_idle (mas_idle),
.afx_m_idle (afx_m_idle),
.slave_idle (slave_idle),
// added for configuration accesses
.pci_slave_mode (pci_slave_mode),
.pci_slave_idsel (pci_slave_idsel),
.pci_clk_sync (pci_clk_sync),
.pci_clk_sync_ (pci_clk_sync_)
);
interrupts interrupts(
.input_reset_l (input_reset_l),
.iu_error (iu_error),
.pci_slave_mode (pci_slave_mode),
.raw_pci_rst_l (raw_pci_rst_l),
.sw_rst (sw_rst),
.en_sw_rst_nonwd (en_sw_rst_nonwd),
.en_pci_sw_rst (en_pci_sw_rst),
.pcim_big_endian (pcim_big_endian),
.pcis_big_endian (pcis_big_endian),
.pci_clk_sync (pci_clk_sync ),
.pci_clk_sync_ (pci_clk_sync_ ),
.gclk_sync (gclk_sync ),
.gclk_sync_ (gclk_sync_ ),
.pci_serr_ (_serr_i ),
.scan_en (csl_scan_mode ),
.reset (reset_reg[0]),
.tmr_clk (tmr_clk),
.clock (gclk),
.pci_clk (pci_clk),
.pci_int_ (ext_int_),
.pci_int_oe (ext_int_oe),
.any_xint (any_xint),
.afx_mast_error_address (afx_mast_error_address),
.afx_mast_error_cmd (afx_mast_error_cmd),
.afx_mast_error (afx_mast_error),
.afx_slave_error (1'b0),
.iotlb_cd_in_reg (iotlb_cd_in_reg),
.iotlb_rd_in_reg (iotlb_rd_in_reg),
.iotlb_cd_out_reg (iotlb_cd_out_reg),
.iotlb_rd_out_reg (iotlb_rd_out_reg),
.iotlb_cntl_reg (iotlb_cntl_reg),
.iotlb_cntl_wrt (iotlb_cntl_wrt),
.iotlb_err (iotlb_err),
.iotlb_err_address (iotlb_err_address),
.iotlb_enable (iotlb_enable),
.irl (falcon_int),
.prefetch_enable (prefetch_enable),
.burst_enable (burst_enable),
.arb_lvl_en (arb_lvl_en),
.arb_disable (arb_disable),
.cfg_fast_decode (cfg_fast_decode),
.afx_master_cfg (afx_master_cfg),
.req_quiescence (req_quiescence),
.ack_quiescence (ack_quiescence),
.discard_timer (discard_timer[15:0]),
.mm_lvl15_int_l (mm_lvl15_int_l),
.any_intrnl_int_l (any_intrnl_int_l),
.smbar0 (smbar0),
.msize0 (msize0),
.pmbar0 (pmbar0),
.smbar1 (smbar1),
.msize1 (msize1),
.pmbar1 (pmbar1),
.sibar (sibar),
.isize (isize),
.pibar (pibar),
.arb_asgn_reg (arb_asgn_reg),
.afx_rd_wrt (afx_rd_wrt),
.pci_config_wdata (pci_config_wdata),
.pci_config_wbe (pci_config_wbe),
.pci_config_wadd (pci_config_wadd),
.pci_config_radd (pci_config_radd),
.pci_config_we (pci_config_we),
.pci_config_rdata (pci_config_rdata),
.cfg_config_out (cfg_config_out)
);
afxmaster afxm(
// add for 2.0 stale data fix
.tar_trdyout (tar_trdyout),
.pcis_big_endian (pcis_big_endian),
.pci_clk_sync (pci_clk_sync ),
.pci_clk_sync_ (pci_clk_sync_ ),
.gclk_sync (gclk_sync ),
.gclk_sync_ (gclk_sync_ ),
.tar_rcv1_fifo_read ( tar_rcv1_fifo_read ),
.tar_rcv_fifo_flush ( tar_rcv_fifo_flush ),
.tar_rcv1_dataout ( tar_rcv1_dataout ),
.tar_rcv1_fifo_be_out ( tar_rcv1_fifo_be_out ),
.tar_rcv1_fifo_next_be_out ( tar_rcv1_fifo_next_be_out ),
.tar_rcv1_fifo_empty ( tar_rcv1_fifo_empty),
.tar_rcv1_fifo_full ( tar_rcv1_fifo_full),
.tar_rcv1_half_full ( tar_rcv1_half_full),
.tar_rcv1_almost_full ( tar_rcv1_almost_full),
.tar_rcv2_fifo_read ( tar_rcv2_fifo_read ),
//.tar_rcv2_fifo_flush ( tar_rcv2_fifo_flush ),
.tar_rcv2_dataout ( tar_rcv2_dataout ),
.tar_rcv2_fifo_be_out ( tar_rcv2_fifo_be_out ),
.tar_rcv2_fifo_next_be_out ( tar_rcv2_fifo_next_be_out ),
.tar_rcv2_fifo_empty ( tar_rcv2_fifo_empty ),
.tar_rcv2_fifo_full ( tar_rcv2_fifo_full),
.tar_rcv2_half_full ( tar_rcv2_half_full),
.tar_rcv2_almost_full ( tar_rcv2_almost_full),
.rcv_fifo_inpempty ( rcv_fifo_inpempty ),
.tar_xmit1_data_in ( tar_xmit1_data_in ),
//.tar_xmit1_data_be_in ( tar_xmit1_data_be_in ),
.tar_xmit1_fifo_write ( tar_xmit1_fifo_write ),
.tar_xmit1_fifo_write_ptr ( tar_xmit1_fifo_write_ptr ),
.tar_xmt_fifo_flush ( tar_xmt_fifo_flush ),
.tar_xmt_fifo_empty ( tar_xmt_fifo_empty ),
.tar_xmt_fifo_outempty ( tar_xmt_fifo_outempty ),
.tar_xmit1_fifo_full ( tar_xmit1_fifo_full ),
.tar_xmit2_data_in ( tar_xmit2_data_in ),
//.tar_xmit2_data_be_in ( tar_xmit2_data_be_in ),
.tar_xmit2_fifo_write ( tar_xmit2_fifo_write ),
.tar_xmit2_fifo_write_ptr ( tar_xmit2_fifo_write_ptr ),
.tar_xmit2_fifo_full ( tar_xmit2_fifo_full ),
.txmt_stop_fifowr ( txmt_stop_fifowr ),
.force_pci_retry ( force_pci_retry ),
.retry_condition ( retry_condition ),
.tar_valid_cmd ( tar_valid_cmd ),
.tar_valid_cmd_early ( tar_valid_cmd_early ),
.afxm_idle_cyc ( afxm_idle_cyc ),
.afxm_dma_read ( afxm_dma_read ),
.afxm_read_alert ( afxm_read_alert ),
.afx_m_idle ( afx_m_idle ),
.cdec_address ( cdec_address ),
.cdec_curCmd ( cdec_curCmd ),
.pclk ( pci_clk ),
// AFX SIGNALS
.am_cstb_l (am_cstb_l),
.am_read (am_read),
.cas_cyc (cas_cyc),
.valid_l (valid_l),
.am_gnt_l (am_gnt_l),
.mm_oddpar (mm_oddpar),
.dp_perr (dp_perr),
.gclk (gclk),
.about (ab_out),
.aboe (pcic_ab_oen),
.dbin (db),
.dbout (db_out2),
.dboe2_in (DBEnable2),
.mparin (mpar),
.mparout (mpar_out2),
.am_wm (am_wm[1:0]),
.reset_l (reset_l_reg),
// MISC SIGNALS
.req_quiescence (req_quiescence),
.ack_quiescence (ack_quiescence),
.req_q_retry (req_q_retry),
.discard_timer (discard_timer[14:0]),
// IOTLB signals
.standby_dsbl_tlb (standby_dsbl_tlb),
.iotlb_cd_in_reg (iotlb_cd_in_reg),
.iotlb_rd_in_reg (iotlb_rd_in_reg),
.iotlb_cd_out_reg (iotlb_cd_out_reg),
.iotlb_rd_out_reg (iotlb_rd_out_reg),
.iotlb_cntl_reg (iotlb_cntl_reg),
.iotlb_cntl_wrt (iotlb_cntl_wrt),
.dma_err (iotlb_err),
.dma_err_address (iotlb_err_address),
.iotlb_enable (iotlb_enable)
);
// RAVICAD CORE
pci_core PCI_CORE (
// PCI Bus Interface
.pci_clk_sync (pci_clk_sync ),
.pci_clk_sync_ (pci_clk_sync_ ),
.gclk_sync (gclk_sync ),
.gclk_sync_ (gclk_sync_ ),
.pci_clk_ (pci_clk_ ),
// This is just for degating async resets to pass TSV, must
// be a +SC not a +SG
.scan_en (csl_scan_mode ),
.AD_out (AD_out ),
.ad_bus_i (ad_bus_i ),
.CBEnnout (CBEnnout ),
.cben_bus_i (cben_bus_i ),
// add the following to fix subword read byte enables
.pci_config_wbe_l (pci_config_wbe_l),
.PAR_out (PAR_out ),
.par_i (par_i ),
.mas_framen_out (mas_framen_out ),
._frame_i (_frame_i ),
._frame_ia (_frame_ia ),
._frame_ib (_frame_ib ),
.mas_irdyn_out (mas_irdyn_out ),
._irdy_i (_irdy_i ),
._irdy_ia (_irdy_ia ),
._irdy_ib (_irdy_ib ),
._irdy_ic (_irdy_ic ),
.perro_ (perro_ ),
._perr_i (_perr_i ),
.serro_ (serro_ ),
._serr_i (_serr_i ),
.tar_devselout (tar_devselout ),
.mas_req_out (mas_req_out ),
._devsel_i (_devsel_i ),
._gnt_i (grant_host_ ),
._lock_i (1'b1 ),
.tar_trdyout (tar_trdyout ),
._trdy_i (_trdy_i ),
._trdy_ia (_trdy_ia ),
._trdy_ib (_trdy_ib ),
.tar_stopout (tar_stopout ),
._stop_i (_stop_i ),
// idsel from bus is not enabled for pci core, only through falcon
// .idsel_i (1'b0 ),
// enable pci configs in pci slave mode
.idsel_i (pci_slave_idsel),
.PCI_rstn_in (PCI_rstn_in ),
.top_ADEnable (top_ADEnable ),
.bot_ADEnable (bot_ADEnable ),
.right_ADEnable (right_ADEnable ),
.cbeEnable (cbeEnable ),
.PAREnable (PAREnable ),
.frameEn (frameEn ),
.trdyEn (trdyEn ),
.irdyEn (irdyEn ),
.stopEn (stopEn ),
.devselEn (devselEn ),
.perrEn (perrEn ),
.serrEnable (serrEnable ),
.pci_clk (pci_clk ),
.app_clk (gclk ),
.reset_l (reset_l_reg ),
.cdec_address ( cdec_address ),
.cdec_curCmd ( cdec_curCmd ),
// .cdec_write_op ( cdec_write_op ),
/*configuration*/
.pci_config_wdata ( pci_config_wdata ),
.pci_config_wbe ( pci_config_wbe),
.pci_config_wadd ( pci_config_wadd ),
.pci_config_radd ( pci_config_radd ),
.pci_config_we ( pci_config_we ),
.pci_config_rdata ( cfg_config_out ),
.cfg_fast_decode ( cfg_fast_decode ),
// add to support pci configuration accesses -
.config_data_out ( pci_config_rdata ),
.config_wbe ( config_wbe ),
.config_add ( config_add ),
.config_data_in ( config_data_in ),
.host_config_access_busy ( host_config_access_busy),
.pci_config_access_busy ( pci_config_access_busy ),
.config_write ( config_write ),
/*dma */
.cmd_out ( cmd_out ),
.address1 ( address1 ),
.wcount1 ( wcount1 ),
/*dma_sm */
.req1 ( req1 ),
// .host_read1 ( host_read1 ),
.mas_start_dma ( mas_start_dma ),
.host1_complete ( host1_complete ),
.host1_fatal ( host1_fatal ),
.host1_perr ( host1_perr ),
.host1_async_perr ( host1_async_perr ),
/* slave */
.force_pci_retry ( force_pci_retry ),
.retry_condition ( retry_condition ),
.tar_valid_cmd ( tar_valid_cmd ),
.tar_valid_cmd_early ( tar_valid_cmd_early ),
.afxm_idle_cyc ( afxm_idle_cyc ),
.afxm_dma_read ( afxm_dma_read ),
.afxm_read_alert ( afxm_read_alert ),
/* master xmit fifo1 */
// .mxmit1_data_in ( mxmit1_data_in ),
// .mxmit1_data_be_in ( mxmit1_data_be_in ),
.mxmt1_fifo_write ( mxmit1_fifo_write ),
.mxmt_fifo_flush ( mas_xmt_fifo_flush ),
.mxmt_data_in ( pci_data_out),
.mxmt_data_be_in ({mxmit2_data_be_in,mxmit1_data_be_in}),
.mxmt_data_last_in (pci_last),
.mxmt2_fifo_write ( mxmit2_fifo_write ),
// .mxmit2_data_in ( mxmit2_data_in ),
// .mxmit2_data_be_in ( mxmit2_data_be_in ),
/* master rcv fifo 1 */
.mrcv1_fifo_read ( mrcv1_fifo_read ),
// .mas_rcv1_dataout ( mas_rcv1_dataout ),
.mrcv1_fifo_empty ( mas_rcv1_fifo_empty ),
// .mas_rcv1_fifo_flush ( mas_rcv_fifo_flush ),
.mrcv_dataout ({mas_rcv2_dataout, mas_rcv1_dataout}),
.mrcv_fifo_flush ( mas_rcv_fifo_flush ),
.mrcv2_fifo_read ( mrcv2_fifo_read ),
// .mas_rcv2_dataout ( mas_rcv2_dataout ),
.mrcv2_fifo_empty ( mas_rcv2_fifo_empty ),
// .mas_rcv2_fifo_flush ( mas_rcv_fifo_flush ),
/* target rcv fifo */
.trcv1_fifo_read ( tar_rcv1_fifo_read ),
.trcv_fifo_flush ( tar_rcv_fifo_flush ),
// .tar_rcv1_dataout ( tar_rcv1_dataout ),
// .tar_rcv1_fifo_be_out ( tar_rcv1_fifo_be_out ),
.trcv1_fifo_empty ( tar_rcv1_fifo_empty),
.trcv1_fifo_full ( tar_rcv1_fifo_full),
.trcv1_half_full ( tar_rcv1_half_full),
.trcv1_almost_full ( tar_rcv1_almost_full),
.trcv_dataout ({tar_rcv2_dataout, tar_rcv1_dataout}),
.trcv_fifo_be_out ({tar_rcv2_fifo_be_out, tar_rcv1_fifo_be_out}),
.trcv_fifo_next_be_out ({tar_rcv2_fifo_next_be_out, tar_rcv1_fifo_next_be_out}),
.trcv2_fifo_read ( tar_rcv2_fifo_read ),
// .trcv2_fifo_flush ( tar_rcv2_fifo_flush ),
// .tar_rcv2_dataout ( tar_rcv2_dataout ),
// .tar_rcv2_fifo_be_out ( tar_rcv2_fifo_be_out ),
.trcv2_fifo_empty ( tar_rcv2_fifo_empty ),
.trcv2_fifo_full ( tar_rcv2_fifo_full),
.trcv2_half_full ( tar_rcv2_half_full),
.trcv2_almost_full ( tar_rcv2_almost_full),
.rcv_fifo_inpempty ( rcv_fifo_inpempty ),
/* target xmt fifo 1 */
// CAUTION BYTE ENABLES NOT HOOKED UP IN PCI CORE!!
// .tar_xmit1_data_in ( tar_xmit1_data_in ),
// .tar_xmit1_data_be_in ( tar_xmit1_data_be_in ),
.txmt1_fifo_write ( tar_xmit1_fifo_write ),
.txmt1_fifo_write_ptr ( tar_xmit1_fifo_write_ptr ),
// .tar_xmit1_fifo_flush ( tar_xmit1_fifo_flush ),
.txmt1_fifo_full ( tar_xmit1_fifo_full ),
.txmt_data_in ( {tar_xmit2_data_in,tar_xmit1_data_in} ),
.txmt_fifo_flush ( tar_xmt_fifo_flush ),
.txmt_fifo_empty ( tar_xmt_fifo_empty ),
.txmt_fifo_outempty ( tar_xmt_fifo_outempty ),
.txmt_stop_fifowr ( txmt_stop_fifowr ),
// .tar_xmit2_data_in ( tar_xmit2_data_in ),
// .tar_xmit2_data_be_in ( tar_xmit2_data_be_in ),
.txmt2_fifo_write ( tar_xmit2_fifo_write ),
.txmt2_fifo_write_ptr ( tar_xmit2_fifo_write_ptr ),
// .tar_xmit2_fifo_flush ( tar_xmit2_fifo_flush ),
.txmt2_fifo_full ( tar_xmit2_fifo_full ),
.req_conf_ ( req_conf_ ),
.grant_conf_ ( grant_conf_ ),
.req_q_retry ( req_q_retry ),
.new_frame ( new_frame ),
.mas_idle ( mas_idle ),
.slave_idle ( slave_idle ),
| This page: |
Created: | Thu Aug 19 12:02:58 1999 |
| From: |
../../../sparc_v8/ssparc/pcic/rtl/pcic.v
|