/******************************************************************************/
/* */
/* Copyright (c) 1999 Sun Microsystems, Inc. All rights reserved. */
/* */
/* The contents of this file are subject to the current version of the Sun */
/* Community Source License, microSPARCII ("the License"). You may not use */
/* this file except in compliance with the License. You may obtain a copy */
/* of the License by searching for "Sun Community Source License" on the */
/* World Wide Web at http://www.sun.com. See the License for the rights, */
/* obligations, and limitations governing use of the contents of this file. */
/* */
/* Sun Microsystems, Inc. has intellectual property rights relating to the */
/* technology embodied in these files. In particular, and without limitation, */
/* these intellectual property rights may include one or more U.S. patents, */
/* foreign patents, or pending applications. */
/* */
/* Sun, Sun Microsystems, the Sun logo, all Sun-based trademarks and logos, */
/* Solaris, Java and all Java-based trademarks and logos are trademarks or */
/* registered trademarks of Sun Microsystems, Inc. in the United States and */
/* other countries. microSPARC is a trademark or registered trademark of */
/* SPARC International, Inc. All SPARC trademarks are used under license and */
/* are trademarks or registered trademarks of SPARC International, Inc. in */
/* the United States and other countries. Products bearing SPARC trademarks */
/* are based upon an architecture developed by Sun Microsystems, Inc. */
/* */
/******************************************************************************/
/*>F****************************************************************************
*** Name: PRIORITY(intpins, irl_in, rand_irl_in, SysClk, irl)
*** Purpose: model interrupt priority encoder.
*** Connections: input intpins - individual source interrupt lines
*** input irl - encoded interrupt level to CPU
*** input SysClk - CPU clock for encoder sequencing
****************************************************************************F<*/
module PRIORITY
(intpins, irl_in, rand_irl_in, SysClk, irl);
/* Interrupt controller ports */
input [15:0] intpins
;
input [3:0] irl_in
;
input [3:0] rand_irl_in
;
input SysClk
;
output [3:0] irl
;
/* Local registers and variables */
reg [3:0] level
[19:0];
reg [3:0] currentlevel
;
reg [7:0] intpending
;
reg [3:0] intreg
;
integer i
;
wire [19:0] internal_intpins
;
assign irl = intreg[3:0];
assign internal_intpins[19:0] = {4'b0000, intpins[15:0]};
initial
begin
level[0] = 1;
level[1] = 3;
level[2] = 5;
level[3] = 7;
level[4] = 9;
level[5] = 11;
level[6] = 14;
level[7] = 0;
level[8] = 0;
level[9] = 0;
level[10] = 0;
level[11] = 0;
level[12] = 0;
level[13] = 0;
level[14] = 0;
level[15] = 15;
level[16] = 0;
level[17] = 0;
level[18] = 0;
level[19] = 0;
intreg = 0;
end
/* Interrupt prioritizer */
always @(negedge SysClk)
begin
level[16] = irl_in;
level[17] = rand_irl_in;
currentlevel = 0;
for (i = 0; i <= 19; i = i + 1)
begin
if (internal_intpins[i] === 0)
begin
if (level[i] > currentlevel) currentlevel = level[i];
end
end
if (intreg != currentlevel)
$display("MSG: PRIORITY: Asserting level %d interrupt\n",
currentlevel);
intreg = currentlevel;
end
endmodule
This page: |
Created: | Thu Aug 19 11:59:45 1999 |
| From: |
../../../sparc_v8/system/rtl/priority.v
|