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/*>F****************************************************************************
***        Name: PRIORITY(intpins, irl_in, rand_irl_in, SysClk, irl)
***     Purpose: model interrupt priority encoder.
*** Connections: input intpins - individual source interrupt lines
***              input irl  - encoded interrupt level to CPU
***              input SysClk - CPU clock for encoder sequencing
****************************************************************************F<*/


module PRIORITY(intpins, irl_in, rand_irl_in, SysClk, irl);

	/*	Interrupt controller ports	*/
	input 	[15:0] 	intpins;
	input 	[3:0] 	irl_in;
	input 	[3:0] 	rand_irl_in;
	input 	 	SysClk;
    	output 	[3:0]	irl;

	/*	Local registers and variables	*/

	reg	[3:0]	level [19:0];
	reg	[3:0]	currentlevel;
	reg	[7:0]	intpending;
	reg	[3:0]	intreg;
	
	integer i;
        wire	[19:0]	internal_intpins;

assign irl = intreg[3:0];
assign internal_intpins[19:0] = {4'b0000, intpins[15:0]};

initial
begin
	level[0] = 1;
	level[1] = 3;
	level[2] = 5;
	level[3] = 7;
	level[4] = 9;
	level[5] = 11;
	level[6] = 14;
	level[7] = 0;
	level[8] = 0;
	level[9] = 0;
	level[10] = 0;
	level[11] = 0;
	level[12] = 0;
	level[13] = 0;
	level[14] = 0;
	level[15] = 15;
	level[16] = 0;
	level[17] = 0;
	level[18] = 0;
	level[19] = 0;

	intreg = 0;
end


	/*	Interrupt prioritizer	*/

	always @(negedge SysClk) 
	    begin
		level[16] = irl_in;
		level[17] = rand_irl_in;
		currentlevel = 0;

	    	for (i = 0; i <= 19; i = i + 1)
	    	begin
		    if (internal_intpins[i] === 0)
		    begin
		        if (level[i] > currentlevel) currentlevel = level[i];
		    end
	    	end
		if (intreg != currentlevel)
		    $display("MSG: PRIORITY: Asserting level %d interrupt\n",
				currentlevel);
		intreg = currentlevel;
	    end
endmodule