/******************************************************************************/
/* */
/* Copyright (c) 1999 Sun Microsystems, Inc. All rights reserved. */
/* */
/* The contents of this file are subject to the current version of the Sun */
/* Community Source License, microSPARCII ("the License"). You may not use */
/* this file except in compliance with the License. You may obtain a copy */
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/* obligations, and limitations governing use of the contents of this file. */
/* */
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/* foreign patents, or pending applications. */
/* */
/* Sun, Sun Microsystems, the Sun logo, all Sun-based trademarks and logos, */
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/* registered trademarks of Sun Microsystems, Inc. in the United States and */
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/* */
/******************************************************************************/
/***************************************************************************
****************************************************************************
***
*** Program File: @(#)quiescent_sm.v
***
***
*** Description:
*** This state machine makes sure execution order is preserved
*** when the cpu and a pci master device try to access the same
*** resource (DRAM) at approximately the same time. It works
*** by receiving a request from the cpu to access a resource.
*** This sm then retries all future PCI DMA requests and waits
*** for the current request to finish, i.e. waits for a quiescent
*** state. It then generates an acknowledge to indicate to the
*** cpu that it can go ahead with its access.
***
*** The handshake between cpu and Falcon is done programmatically,
*** i.e., through a software-writeable/readable status register in
*** Falcon.
***
****************************************************************************
****************************************************************************/
`define Q_IDLE 2'b00
`define REQ_Q 2'b01
`define WAIT4Q 2'b11
`define QUIESCENT 2'b10
`timescale 1ns/1ns
module quiescent_sm
(ack_quiescence, req_q_rd,
req_quiescence, clk, reset_l, tar_valid_cmd, read_alert,
trcv_empty_p, txmt_empty_p, delayed_read, retry_addr_match,
idle_cyc_p
);
output ack_quiescence
;
output req_q_rd
;
input req_quiescence
;
input clk
;
input reset_l
;
input tar_valid_cmd
;
input read_alert
;
input trcv_empty_p
;
input txmt_empty_p
;
input delayed_read
;
input retry_addr_match
;
input idle_cyc_p
;
wire [1:0] q_state
; // curr state of q_sm
function [1:0] q_sm;
input [1:0] q_state;
input reset_l; // system or PCI reset_l
input req_quiescence;
input tar_valid_cmd;
input read_alert;
input trcv_empty_p;
input txmt_empty_p;
input delayed_read;
input retry_addr_match;
input idle_cyc_p;
reg [1:0] q_ns; // next_state
begin
if (~reset_l) begin
q_ns = `Q_IDLE;
end
else begin
q_ns = q_state;
case (q_state)
`Q_IDLE: begin
if (req_quiescence)
q_ns = `REQ_Q;
else
q_ns = `Q_IDLE;
end
`REQ_Q: begin
if (idle_cyc_p & trcv_empty_p & ~tar_valid_cmd &
(txmt_empty_p | ~retry_addr_match))
q_ns = `QUIESCENT;
else
q_ns = `WAIT4Q;
end
`WAIT4Q: begin
if (idle_cyc_p & trcv_empty_p & ~tar_valid_cmd )
//(txmt_empty_p | ~retry_addr_match))
q_ns = `QUIESCENT;
else
q_ns = `WAIT4Q;
end
`QUIESCENT: begin
if (~req_quiescence)
q_ns = `Q_IDLE;
else
q_ns = `QUIESCENT;
end
default: begin
q_ns = `Q_IDLE;
//synopsys translate_off
if (reset_l) $display("q_sm: Error!");
//synopsys translate_on
end
endcase
end
q_sm = q_ns;
end
endfunction
reg [1:0] sm_output
;
always @(posedge clk) begin
if (~reset_l)
sm_output[1:0] <= #1 `Q_IDLE;
else
sm_output[1:0] <= #1 q_sm(q_state, reset_l, req_quiescence,
tar_valid_cmd, read_alert, trcv_empty_p,
txmt_empty_p, delayed_read, retry_addr_match,
idle_cyc_p);
end
assign q_state[1:0] = sm_output[1:0];
wire ack_quiescence = (q_state==`QUIESCENT);
wire req_q_rd = (q_state==`WAIT4Q);
endmodule
This page: |
Created: | Thu Aug 19 12:00:30 1999 |
| From: |
../../../sparc_v8/ssparc/pcic/afxmaster/rtl/quiescent_sm.v
|