/******************************************************************************/
/* */
/* Copyright (c) 1999 Sun Microsystems, Inc. All rights reserved. */
/* */
/* The contents of this file are subject to the current version of the Sun */
/* Community Source License, microSPARCII ("the License"). You may not use */
/* this file except in compliance with the License. You may obtain a copy */
/* of the License by searching for "Sun Community Source License" on the */
/* World Wide Web at http://www.sun.com. See the License for the rights, */
/* obligations, and limitations governing use of the contents of this file. */
/* */
/* Sun Microsystems, Inc. has intellectual property rights relating to the */
/* technology embodied in these files. In particular, and without limitation, */
/* these intellectual property rights may include one or more U.S. patents, */
/* foreign patents, or pending applications. */
/* */
/* Sun, Sun Microsystems, the Sun logo, all Sun-based trademarks and logos, */
/* Solaris, Java and all Java-based trademarks and logos are trademarks or */
/* registered trademarks of Sun Microsystems, Inc. in the United States and */
/* other countries. microSPARC is a trademark or registered trademark of */
/* SPARC International, Inc. All SPARC trademarks are used under license and */
/* are trademarks or registered trademarks of SPARC International, Inc. in */
/* the United States and other countries. Products bearing SPARC trademarks */
/* are based upon an architecture developed by Sun Microsystems, Inc. */
/* */
/******************************************************************************/
// *************************************************************************
// @(#)rl_memif_minor.v 1.1 10/15/93
// rl_memif_minor.v
//
// Description:
// The Data Path Controller block of memory subsystem in SingleSPARC.
// Refer to SingleSPARC Hardware Spec, section 2.7.4 for block diagram
// and more information.
//
//
// Dependencies:
// mem_cells.vpp defines.v dpc_bi_tri.v dpc_core.v
// dpc_logic.v dpc_cont.v dpc_par.v dpc_dpath.v
//
//
//
// *************************************************************************
// *************************************************************************
// This is the the DPC block. It has all the inter-block connections,
// the 3-state buffers and bi-dir pads.
module rl_memif_minor
(bd_mux_out1, bd_mux_out0,
quad_sel_dwd, quad_sel_dwd_1, quad_sel,
mc_mdata_in, out_hld_2, out_hld_3,
ss_clock );
output [31:0] bd_mux_out1
;
output [31:0] bd_mux_out0
;
input [31:0] mc_mdata_in
;
input quad_sel_dwd
;
input quad_sel_dwd_1
;
input quad_sel
;
input out_hld_2
;
input out_hld_3
;
input ss_clock
;
wire [63:0] quad_data
;
// wire quad_sel_dwd;
// assign quad_sel_dwd = prev_wd_sel | quad_sel;
Mux2_32 out1_mux (bd_mux_out1[31:0],mc_mdata_in[31:0],
quad_data[63:32], quad_sel_dwd);
Mux2_32 out0_mux (bd_mux_out0[31:0], mc_mdata_in[31:0],
quad_data[31:0], quad_sel);
GReg32 out2 (quad_data[63:32] , mc_mdata_in[31:0] , ss_clock ,
out_hld_2);
GReg32 out3 (quad_data[31:0] , mc_mdata_in[31:0] , ss_clock ,
out_hld_3);
endmodule
This page: |
Created: | Thu Aug 19 12:03:11 1999 |
| From: |
../../../sparc_v8/ssparc/memif/rtl/rl_memif_minor.v
|