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/* Copyright (c) 1999 Sun Microsystems, Inc. All rights reserved. */
/* */
/* The contents of this file are subject to the current version of the Sun */
/* Community Source License, microSPARCII ("the License"). You may not use */
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/******************************************************************************/
// timescale 1ns / 1ns
//---------------------------------------------------------------------------
// @(#)mem_cells.v 1.7 3/10/93
// mem_cells.v
//
// Description:
// The larger primitive blocks like 16-64 bit wide registers, muxes, etc
// reside in this file.
// Most of the modules defined here, are based on the basic cells
// defined in "cells.h" or are library parts.
//
// Dependencies:
// Must be passed through the "cpp" and "m4" preprocessors after "cells.h"
// is pre-pended to it.
//
//
//
//---------------------------------------------------------------------------
//----------------------------------------------------------------------------
// 64 bit byte-wize 2:1 Mux, with single select for each byte.
// based on MUX2 of cells.h.
![[Up: rl_dpc_dpath dmux]](v2html-up.gif)
module Mux8x8_2to1
(out , ina , inb , sela);
output [63:0] out;
input [63:0] ina, inb;
input [ 7:0] sela; // When high, ina' is selected.
wire [63:0] out;
// Expanded macro begin.
// cmux2(Mux2Byte7, 8, out[63:56], inb[63:56], ina[63:56], sela[7])
function [8:1] Mux2Byte7 ;
input [8:1] in0_fn ;
input [8:1] in1_fn ;
input select_fn ;
reg [8:1] out_fn ;
begin
case (select_fn) /* synopsys parallel_case */
1'b0: out_fn = in0_fn ;
1'b1: out_fn = in1_fn ;
default: out_fn = 65'hx;
endcase
Mux2Byte7 = out_fn ;
end
endfunction
assign out[63:56] = Mux2Byte7(inb[63:56], ina[63:56], sela[7]) ;
// Expanded macro end.
// Expanded macro begin.
// cmux2(Mux2Byte6, 8, out[55:48], inb[55:48], ina[55:48], sela[6])
function [8:1] Mux2Byte6 ;
input [8:1] in0_fn ;
input [8:1] in1_fn ;
input select_fn ;
reg [8:1] out_fn ;
begin
case (select_fn) /* synopsys parallel_case */
1'b0: out_fn = in0_fn ;
1'b1: out_fn = in1_fn ;
default: out_fn = 65'hx;
endcase
Mux2Byte6 = out_fn ;
end
endfunction
assign out[55:48] = Mux2Byte6(inb[55:48], ina[55:48], sela[6]) ;
// Expanded macro end.
// Expanded macro begin.
// cmux2(Mux2Byte5, 8, out[47:40], inb[47:40], ina[47:40], sela[5])
function [8:1] Mux2Byte5 ;
input [8:1] in0_fn ;
input [8:1] in1_fn ;
input select_fn ;
reg [8:1] out_fn ;
begin
case (select_fn) /* synopsys parallel_case */
1'b0: out_fn = in0_fn ;
1'b1: out_fn = in1_fn ;
default: out_fn = 65'hx;
endcase
Mux2Byte5 = out_fn ;
end
endfunction
assign out[47:40] = Mux2Byte5(inb[47:40], ina[47:40], sela[5]) ;
// Expanded macro end.
// Expanded macro begin.
// cmux2(Mux2Byte4, 8, out[39:32], inb[39:32], ina[39:32], sela[4])
function [8:1] Mux2Byte4 ;
input [8:1] in0_fn ;
input [8:1] in1_fn ;
input select_fn ;
reg [8:1] out_fn ;
begin
case (select_fn) /* synopsys parallel_case */
1'b0: out_fn = in0_fn ;
1'b1: out_fn = in1_fn ;
default: out_fn = 65'hx;
endcase
Mux2Byte4 = out_fn ;
end
endfunction
assign out[39:32] = Mux2Byte4(inb[39:32], ina[39:32], sela[4]) ;
// Expanded macro end.
// Expanded macro begin.
// cmux2(Mux2Byte3, 8, out[31:24], inb[31:24], ina[31:24], sela[3])
function [8:1] Mux2Byte3 ;
input [8:1] in0_fn ;
input [8:1] in1_fn ;
input select_fn ;
reg [8:1] out_fn ;
begin
case (select_fn) /* synopsys parallel_case */
1'b0: out_fn = in0_fn ;
1'b1: out_fn = in1_fn ;
default: out_fn = 65'hx;
endcase
Mux2Byte3 = out_fn ;
end
endfunction
assign out[31:24] = Mux2Byte3(inb[31:24], ina[31:24], sela[3]) ;
// Expanded macro end.
// Expanded macro begin.
// cmux2(Mux2Byte2, 8, out[23:16], inb[23:16], ina[23:16], sela[2])
function [8:1] Mux2Byte2 ;
input [8:1] in0_fn ;
input [8:1] in1_fn ;
input select_fn ;
reg [8:1] out_fn ;
begin
case (select_fn) /* synopsys parallel_case */
1'b0: out_fn = in0_fn ;
1'b1: out_fn = in1_fn ;
default: out_fn = 65'hx;
endcase
Mux2Byte2 = out_fn ;
end
endfunction
assign out[23:16] = Mux2Byte2(inb[23:16], ina[23:16], sela[2]) ;
// Expanded macro end.
// Expanded macro begin.
// cmux2(Mux2Byte1, 8, out[15: 8], inb[15: 8], ina[15: 8], sela[1])
function [8:1] Mux2Byte1 ;
input [8:1] in0_fn ;
input [8:1] in1_fn ;
input select_fn ;
reg [8:1] out_fn ;
begin
case (select_fn) /* synopsys parallel_case */
1'b0: out_fn = in0_fn ;
1'b1: out_fn = in1_fn ;
default: out_fn = 65'hx;
endcase
Mux2Byte1 = out_fn ;
end
endfunction
assign out[15: 8] = Mux2Byte1(inb[15: 8], ina[15: 8], sela[1]) ;
// Expanded macro end.
// Expanded macro begin.
// cmux2(Mux2Byte0, 8, out[ 7: 0], inb[ 7: 0], ina[ 7: 0], sela[0])
function [8:1] Mux2Byte0 ;
input [8:1] in0_fn ;
input [8:1] in1_fn ;
input select_fn ;
reg [8:1] out_fn ;
begin
case (select_fn) /* synopsys parallel_case */
1'b0: out_fn = in0_fn ;
1'b1: out_fn = in1_fn ;
default: out_fn = 65'hx;
endcase
Mux2Byte0 = out_fn ;
end
endfunction
assign out[ 7: 0] = Mux2Byte0(inb[ 7: 0], ina[ 7: 0], sela[0]) ;
// Expanded macro end.
endmodule
//----------------------------------------------------------------------------
// 1-bit 2:1 Mux, based on MUX2 of cells.h.
module Mux2_1(out, in0, in1, sel1);
output out;
input in0, in1;
input sel1; // Select in1 when high, select in0 when low.
wire out;
// Expanded macro begin.
// cmux2(Mux2_1bit, 1, out, in0, in1, sel1)
function [1:1] Mux2_1bit ;
input [1:1] in0_fn ;
input [1:1] in1_fn ;
input select_fn ;
reg [1:1] out_fn ;
begin
case (select_fn) /* synopsys parallel_case */
1'b0: out_fn = in0_fn ;
1'b1: out_fn = in1_fn ;
default: out_fn = 65'hx;
endcase
Mux2_1bit = out_fn ;
end
endfunction
assign out = Mux2_1bit(in0, in1, sel1) ;
// Expanded macro end.
endmodule
//----------------------------------------------------------------------------
// 2-bit 2:1 Mux, based on MUX2 of cells.h.
module Mux2_2(out, in0, in1, sel1);
output [1:0] out;
input [1:0] in0, in1;
input sel1; // Select in1 when high, select in0 when low.
wire [1:0] out;
// Expanded macro begin.
// cmux2(Mux2_2bit, 2, out[1:0], in0[1:0], in1[1:0], sel1)
function [2:1] Mux2_2bit ;
input [2:1] in0_fn ;
input [2:1] in1_fn ;
input select_fn ;
reg [2:1] out_fn ;
begin
case (select_fn) /* synopsys parallel_case */
1'b0: out_fn = in0_fn ;
1'b1: out_fn = in1_fn ;
default: out_fn = 65'hx;
endcase
Mux2_2bit = out_fn ;
end
endfunction
assign out[1:0] = Mux2_2bit(in0[1:0], in1[1:0], sel1) ;
// Expanded macro end.
endmodule
//----------------------------------------------------------------------------
// 3-bit 2:1 Mux, based on MUX2 of cells.h.
module Mux2_3(out, in0, in1, sel1);
output [2:0] out;
input [2:0] in0, in1;
input sel1; // Select in1 when high, select in0 when low.
wire [2:0] out;
// Expanded macro begin.
// cmux2(Mux2_3bit, 3, out[2:0], in0[2:0], in1[2:0], sel1)
function [3:1] Mux2_3bit ;
input [3:1] in0_fn ;
input [3:1] in1_fn ;
input select_fn ;
reg [3:1] out_fn ;
begin
case (select_fn) /* synopsys parallel_case */
1'b0: out_fn = in0_fn ;
1'b1: out_fn = in1_fn ;
default: out_fn = 65'hx;
endcase
Mux2_3bit = out_fn ;
end
endfunction
assign out[2:0] = Mux2_3bit(in0[2:0], in1[2:0], sel1) ;
// Expanded macro end.
endmodule
//----------------------------------------------------------------------------
// 6-bit 2:1 Mux, based on MUX2 of cells.h.
module Mux2_6(out, in0, in1, sel1);
output [5:0] out;
input [5:0] in0, in1;
input sel1; // Select in1 when high, select in0 when low.
wire [5:0] out;
// Expanded macro begin.
// cmux2(Mux2_6bit, 6, out[5:0], in0[5:0], in1[5:0], sel1)
function [6:1] Mux2_6bit ;
input [6:1] in0_fn ;
input [6:1] in1_fn ;
input select_fn ;
reg [6:1] out_fn ;
begin
case (select_fn) /* synopsys parallel_case */
1'b0: out_fn = in0_fn ;
1'b1: out_fn = in1_fn ;
default: out_fn = 65'hx;
endcase
Mux2_6bit = out_fn ;
end
endfunction
assign out[5:0] = Mux2_6bit(in0[5:0], in1[5:0], sel1) ;
// Expanded macro end.
endmodule
//----------------------------------------------------------------------------
// 9-bit 2:1 Mux, based on MUX2 of cells.h.
module Mux2_9(out, in0, in1, sel1);
output [8:0] out;
input [8:0] in0, in1;
input sel1; // Select in1 when high, select in0 when low.
wire [8:0] out;
// Expanded macro begin.
// cmux2(Mux2_9bit, 9, out[8:0], in0[8:0], in1[8:0], sel1)
function [9:1] Mux2_9bit ;
input [9:1] in0_fn ;
input [9:1] in1_fn ;
input select_fn ;
reg [9:1] out_fn ;
begin
case (select_fn) /* synopsys parallel_case */
1'b0: out_fn = in0_fn ;
1'b1: out_fn = in1_fn ;
default: out_fn = 65'hx;
endcase
Mux2_9bit = out_fn ;
end
endfunction
assign out[8:0] = Mux2_9bit(in0[8:0], in1[8:0], sel1) ;
// Expanded macro end.
endmodule
//----------------------------------------------------------------------------
// 11-bit 2:1 Mux, based on MUX2 of cells.h.
module Mux2_11(out, in0, in1, sel1);
output [10:0] out;
input [10:0] in0, in1;
input sel1; // Select in1 when high, select in0 when low.
wire [10:0] out;
// Expanded macro begin.
// cmux2(Mux2_11bit, 11, out[10:0], in0[10:0], in1[10:0], sel1)
function [11:1] Mux2_11bit ;
input [11:1] in0_fn ;
input [11:1] in1_fn ;
input select_fn ;
reg [11:1] out_fn ;
begin
case (select_fn) /* synopsys parallel_case */
1'b0: out_fn = in0_fn ;
1'b1: out_fn = in1_fn ;
default: out_fn = 65'hx;
endcase
Mux2_11bit = out_fn ;
end
endfunction
assign out[10:0] = Mux2_11bit(in0[10:0], in1[10:0], sel1) ;
// Expanded macro end.
endmodule
//----------------------------------------------------------------------------
// 32-bit 2:1 Mux, based on MUX2 of cells.h.
module Mux2_32(out, in0, in1, sel1);
output [31:0] out;
input [31:0] in0, in1;
input sel1; // Select in1 when high, select in0 when low.
wire [31:0] out;
// Expanded macro begin.
// cmux2(Mux2_32bit, 32, out[31:0], in0[31:0], in1[31:0], sel1)
function [32:1] Mux2_32bit ;
input [32:1] in0_fn ;
input [32:1] in1_fn ;
input select_fn ;
reg [32:1] out_fn ;
begin
case (select_fn) /* synopsys parallel_case */
1'b0: out_fn = in0_fn ;
1'b1: out_fn = in1_fn ;
default: out_fn = 65'hx;
endcase
Mux2_32bit = out_fn ;
end
endfunction
assign out[31:0] = Mux2_32bit(in0[31:0], in1[31:0], sel1) ;
// Expanded macro end.
endmodule
//----------------------------------------------------------------------------
// 2-bit 3:1 Mux, based on MUX3D of cells.h.
module Mux3D_1(out, in0, sel0, in1, sel1, in2, sel2);
output out;
input in0, in1, in2;
input sel0, sel1, sel2;
wire out;
// Expanded macro begin.
// cmux3d(Mux3D_1bit, 1, out, in0, sel0, in1, sel1, in2, sel2)
function [1:1] Mux3D_1bit ;
input [1:1] in0_fn ;
input s0_fn ;
input [1:1] in1_fn ;
input s1_fn ;
input [1:1] in2_fn ;
input s2_fn ;
reg [1:1] out_fn ;
begin
case ({sel2, sel1, sel0}) /* synopsys parallel_case */
3'b001: out_fn = in0_fn;
3'b010: out_fn = in1_fn;
3'b100: out_fn = in2_fn;
default: out_fn = 65'hx;
endcase
Mux3D_1bit = out_fn ;
end
endfunction
assign out = Mux3D_1bit(in0, sel0, in1, sel1, in2, sel2) ;
// synopsys translate_off
always @ (posedge(~Mclocks.clock))
#1 if ((sel2+sel1+sel0 !== 1) & `SS_SCOPE.input_reset_l &
~Mtask.trace.ppr & ~(sel2+sel1^sel0===1'bx)) begin
$display("### %m.Mux3D_1bit: CMUX3D select error!\n");
$display("sel2,sel1,sel0=%0d%0d%0d\n", sel2,sel1,sel0);
Mclocks.warning_count = Mclocks.warning_count + 1;
end
// synopsys translate_on
// Expanded macro end.
endmodule
//----------------------------------------------------------------------------
module Mux3D_2(out, in0, sel0, in1, sel1, in2, sel2);
output [1:0] out;
input [1:0] in0, in1, in2;
input sel0, sel1, sel2;
wire [1:0] out;
// Expanded macro begin.
// cmux3d(Mux3D_2bit, 2, out[1:0], in0[1:0], sel0, in1[1:0], sel1, in2[1:0], sel2)
function [2:1] Mux3D_2bit ;
input [2:1] in0_fn ;
input s0_fn ;
input [2:1] in1_fn ;
input s1_fn ;
input [2:1] in2_fn ;
input s2_fn ;
reg [2:1] out_fn ;
begin
case ({sel2, sel1, sel0}) /* synopsys parallel_case */
3'b001: out_fn = in0_fn;
3'b010: out_fn = in1_fn;
3'b100: out_fn = in2_fn;
default: out_fn = 65'hx;
endcase
Mux3D_2bit = out_fn ;
end
endfunction
assign out[1:0] = Mux3D_2bit(in0[1:0], sel0, in1[1:0], sel1, in2[1:0], sel2) ;
// synopsys translate_off
always @ (posedge(~Mclocks.clock))
#1 if ((sel2+sel1+sel0 !== 1) & `SS_SCOPE.input_reset_l &
~Mtask.trace.ppr & ~(sel2+sel1^sel0===1'bx)) begin
$display("### %m.Mux3D_2bit: CMUX3D select error!\n");
$display("sel2,sel1,sel0=%0d%0d%0d\n", sel2,sel1,sel0);
Mclocks.warning_count = Mclocks.warning_count + 1;
end
// synopsys translate_on
// Expanded macro end.
endmodule
//----------------------------------------------------------------------------
// 3-bit 3:1 Mux, based on MUX3D of cells.h.
module Mux3D_3(out, in0, sel0, in1, sel1, in2, sel2);
output [2:0] out;
input [2:0] in0, in1, in2;
input sel0, sel1, sel2;
wire [2:0] out;
// Expanded macro begin.
// cmux3d(Mux3D_3bit, 3, out[2:0], in0[2:0], sel0, in1[2:0], sel1, in2[2:0], sel2)
function [3:1] Mux3D_3bit ;
input [3:1] in0_fn ;
input s0_fn ;
input [3:1] in1_fn ;
input s1_fn ;
input [3:1] in2_fn ;
input s2_fn ;
reg [3:1] out_fn ;
begin
case ({sel2, sel1, sel0}) /* synopsys parallel_case */
3'b001: out_fn = in0_fn;
3'b010: out_fn = in1_fn;
3'b100: out_fn = in2_fn;
default: out_fn = 65'hx;
endcase
Mux3D_3bit = out_fn ;
end
endfunction
assign out[2:0] = Mux3D_3bit(in0[2:0], sel0, in1[2:0], sel1, in2[2:0], sel2) ;
// synopsys translate_off
always @ (posedge(~Mclocks.clock))
#1 if ((sel2+sel1+sel0 !== 1) & `SS_SCOPE.input_reset_l &
~Mtask.trace.ppr & ~(sel2+sel1^sel0===1'bx)) begin
$display("### %m.Mux3D_3bit: CMUX3D select error!\n");
$display("sel2,sel1,sel0=%0d%0d%0d\n", sel2,sel1,sel0);
Mclocks.warning_count = Mclocks.warning_count + 1;
end
// synopsys translate_on
// Expanded macro end.
endmodule
//----------------------------------------------------------------------------
// 11-bit 3:1 Mux, based on MUX3D of cells.h.
module Mux3D_11(out, in0, sel0, in1, sel1, in2, sel2);
output [10:0] out;
input [10:0] in0, in1, in2;
input sel0, sel1, sel2;
wire [10:0] out;
// Expanded macro begin.
// cmux3d(Mux3D_11bit, 11, out[10:0], in0[10:0], sel0, in1[10:0], sel1, in2[10:0], sel2)
function [11:1] Mux3D_11bit ;
input [11:1] in0_fn ;
input s0_fn ;
input [11:1] in1_fn ;
input s1_fn ;
input [11:1] in2_fn ;
input s2_fn ;
reg [11:1] out_fn ;
begin
case ({sel2, sel1, sel0}) /* synopsys parallel_case */
3'b001: out_fn = in0_fn;
3'b010: out_fn = in1_fn;
3'b100: out_fn = in2_fn;
default: out_fn = 65'hx;
endcase
Mux3D_11bit = out_fn ;
end
endfunction
assign out[10:0] = Mux3D_11bit(in0[10:0], sel0, in1[10:0], sel1, in2[10:0], sel2) ;
// synopsys translate_off
always @ (posedge(~Mclocks.clock))
#1 if ((sel2+sel1+sel0 !== 1) & `SS_SCOPE.input_reset_l &
~Mtask.trace.ppr & ~(sel2+sel1^sel0===1'bx)) begin
$display("### %m.Mux3D_11bit: CMUX3D select error!\n");
$display("sel2,sel1,sel0=%0d%0d%0d\n", sel2,sel1,sel0);
Mclocks.warning_count = Mclocks.warning_count + 1;
end
// synopsys translate_on
// Expanded macro end.
endmodule
//----------------------------------------------------------------------------
// 32-bit 3:1 Mux, based on MUX3D of cells.h.
module Mux3D_32(out, in0, sel0, in1, sel1, in2, sel2);
output [31:0] out;
input [31:0] in0, in1, in2;
input sel0, sel1, sel2;
wire [31:0] out;
// Expanded macro begin.
// cmux3d(Mux3D_32bit, 32, out[31:0], in0[31:0], sel0, in1[31:0], sel1, in2[31:0], sel2)
function [32:1] Mux3D_32bit ;
input [32:1] in0_fn ;
input s0_fn ;
input [32:1] in1_fn ;
input s1_fn ;
input [32:1] in2_fn ;
input s2_fn ;
reg [32:1] out_fn ;
begin
case ({sel2, sel1, sel0}) /* synopsys parallel_case */
3'b001: out_fn = in0_fn;
3'b010: out_fn = in1_fn;
3'b100: out_fn = in2_fn;
default: out_fn = 65'hx;
endcase
Mux3D_32bit = out_fn ;
end
endfunction
assign out[31:0] = Mux3D_32bit(in0[31:0], sel0, in1[31:0], sel1, in2[31:0], sel2) ;
// synopsys translate_off
always @ (posedge(~Mclocks.clock))
#1 if ((sel2+sel1+sel0 !== 1) & `SS_SCOPE.input_reset_l &
~Mtask.trace.ppr & ~(sel2+sel1^sel0===1'bx)) begin
$display("### %m.Mux3D_32bit: CMUX3D select error!\n");
$display("sel2,sel1,sel0=%0d%0d%0d\n", sel2,sel1,sel0);
Mclocks.warning_count = Mclocks.warning_count + 1;
end
// synopsys translate_on
// Expanded macro end.
endmodule
//----------------------------------------------------------------------------
// 1-bit 4:1 Mux, based on MUX4D of cells.h.
module Mux4D_1(out, in0, sel0, in1, sel1, in2, sel2, in3, sel3);
output out;
input in0, in1, in2, in3;
input sel0, sel1, sel2, sel3;
wire out;
// Expanded macro begin.
// cmux4d(Mux4D_1bit, 1, out, in0, sel0, in1, sel1, in2, sel2, in3, sel3)
function [1:1] Mux4D_1bit ;
input [1:1] in0_fn ;
input s0_fn ;
input [1:1] in1_fn ;
input s1_fn ;
input [1:1] in2_fn ;
input s2_fn ;
input [1:1] in3_fn ;
input s3_fn ;
reg [1:1] out_fn ;
begin
case ({sel3, sel2, sel1, sel0}) /* synopsys parallel_case */
4'b0001: out_fn = in0_fn;
4'b0010: out_fn = in1_fn;
4'b0100: out_fn = in2_fn;
4'b1000: out_fn = in3_fn;
default: out_fn = 65'hx;
endcase
Mux4D_1bit = out_fn ;
end
endfunction
assign out = Mux4D_1bit(in0, sel0, in1, sel1, in2, sel2, in3, sel3) ;
// synopsys translate_off
always @ (posedge(~Mclocks.clock))
#1 if ((sel3+sel2+sel1+sel0 !== 1) & `SS_SCOPE.input_reset_l &
~Mtask.trace.ppr & ~(sel3+sel2+sel1^sel0===1'bx)) begin
$display("### %m.Mux4D_1bit: CMUX4D select error!\n");
$display("sel3,sel2,sel1,sel0=%0d%0d%0d%0d\n", sel3,sel2,sel1,sel0);
Mclocks.warning_count = Mclocks.warning_count + 1;
end
// synopsys translate_on
// Expanded macro end.
endmodule
//----------------------------------------------------------------------------
// 2-bit 4:1 Mux, based on MUX4D of cells.h.
module Mux4D_2(out, in0, sel0, in1, sel1, in2, sel2, in3, sel3);
output [1:0] out;
input [1:0] in0, in1, in2, in3;
input sel0, sel1, sel2, sel3;
wire [1:0] out;
// Expanded macro begin.
// cmux4d(Mux4D_2bit, 2, out[1:0], in0[1:0], sel0, in1[1:0], sel1, in2[1:0], sel2, in3[1:0], sel3)
function [2:1] Mux4D_2bit ;
input [2:1] in0_fn ;
input s0_fn ;
input [2:1] in1_fn ;
input s1_fn ;
input [2:1] in2_fn ;
input s2_fn ;
input [2:1] in3_fn ;
input s3_fn ;
reg [2:1] out_fn ;
begin
case ({sel3, sel2, sel1, sel0}) /* synopsys parallel_case */
4'b0001: out_fn = in0_fn;
4'b0010: out_fn = in1_fn;
4'b0100: out_fn = in2_fn;
4'b1000: out_fn = in3_fn;
default: out_fn = 65'hx;
endcase
Mux4D_2bit = out_fn ;
end
endfunction
assign out[1:0] = Mux4D_2bit(in0[1:0], sel0, in1[1:0], sel1, in2[1:0], sel2, in3[1:0], sel3) ;
// synopsys translate_off
always @ (posedge(~Mclocks.clock))
#1 if ((sel3+ sel2+sel1+sel0 !== 1) & `SS_SCOPE.input_reset_l &
~Mtask.trace.ppr & ~(sel3+ sel2+sel1^sel0===1'bx)) begin
$display("### %m.Mux4D_2bit: CMUX4D select error!\n");
$display("sel3, sel2,sel1,sel0=%0d%0d%0d%0d\n", sel3, sel2,sel1,sel0);
Mclocks.warning_count = Mclocks.warning_count + 1;
end
// synopsys translate_on
// Expanded macro end.
endmodule
//----------------------------------------------------------------------------
// 4-bit 4:1 Mux, based on MUX4D of cells.h.
module Mux4D_4(out, in0, sel0, in1, sel1, in2, sel2, in3, sel3);
output [3:0] out;
input [3:0] in0, in1, in2, in3;
input sel0, sel1, sel2, sel3;
wire [3:0] out;
// Expanded macro begin.
// cmux4d(Mux4D_4bit, 4, out[3:0], in0[3:0], sel0, in1[3:0], sel1, in2[3:0], sel2, in3[3:0], sel3)
function [4:1] Mux4D_4bit ;
input [4:1] in0_fn ;
input s0_fn ;
input [4:1] in1_fn ;
input s1_fn ;
input [4:1] in2_fn ;
input s2_fn ;
input [4:1] in3_fn ;
input s3_fn ;
reg [4:1] out_fn ;
begin
case ({sel3, sel2, sel1, sel0}) /* synopsys parallel_case */
4'b0001: out_fn = in0_fn;
4'b0010: out_fn = in1_fn;
4'b0100: out_fn = in2_fn;
4'b1000: out_fn = in3_fn;
default: out_fn = 65'hx;
endcase
Mux4D_4bit = out_fn ;
end
endfunction
assign out[3:0] = Mux4D_4bit(in0[3:0], sel0, in1[3:0], sel1, in2[3:0], sel2, in3[3:0], sel3) ;
// synopsys translate_off
always @ (posedge(~Mclocks.clock))
#1 if ((sel3+ sel2+sel1+sel0 !== 1) & `SS_SCOPE.input_reset_l &
~Mtask.trace.ppr & ~(sel3+ sel2+sel1^sel0===1'bx)) begin
$display("### %m.Mux4D_4bit: CMUX4D select error!\n");
$display("sel3, sel2,sel1,sel0=%0d%0d%0d%0d\n", sel3, sel2,sel1,sel0);
Mclocks.warning_count = Mclocks.warning_count + 1;
end
// synopsys translate_on
// Expanded macro end.
endmodule
//----------------------------------------------------------------------------
// 11-bit 4:1 Mux, based on MUX4D of cells.h.
module Mux4D_11(out, in0, sel0, in1, sel1, in2, sel2, in3, sel3);
output [10:0] out;
input [10:0] in0, in1, in2, in3;
input sel0, sel1, sel2, sel3;
wire [10:0] out;
// Expanded macro begin.
// cmux4d(Mux4D_11bit, 11, out[10:0], in0[10:0], sel0, in1[10:0], sel1, in2[10:0], sel2, in3[10:0], sel3)
function [11:1] Mux4D_11bit ;
input [11:1] in0_fn ;
input s0_fn ;
input [11:1] in1_fn ;
input s1_fn ;
input [11:1] in2_fn ;
input s2_fn ;
input [11:1] in3_fn ;
input s3_fn ;
reg [11:1] out_fn ;
begin
case ({sel3, sel2, sel1, sel0}) /* synopsys parallel_case */
4'b0001: out_fn = in0_fn;
4'b0010: out_fn = in1_fn;
4'b0100: out_fn = in2_fn;
4'b1000: out_fn = in3_fn;
default: out_fn = 65'hx;
endcase
Mux4D_11bit = out_fn ;
end
endfunction
assign out[10:0] = Mux4D_11bit(in0[10:0], sel0, in1[10:0], sel1, in2[10:0], sel2, in3[10:0], sel3) ;
// synopsys translate_off
always @ (posedge(~Mclocks.clock))
#1 if ((sel3+ sel2+sel1+sel0 !== 1) & `SS_SCOPE.input_reset_l &
~Mtask.trace.ppr & ~(sel3+ sel2+sel1^sel0===1'bx)) begin
$display("### %m.Mux4D_11bit: CMUX4D select error!\n");
$display("sel3, sel2,sel1,sel0=%0d%0d%0d%0d\n", sel3, sel2,sel1,sel0);
Mclocks.warning_count = Mclocks.warning_count + 1;
end
// synopsys translate_on
// Expanded macro end.
endmodule
//----------------------------------------------------------------------------
// 1-bit gated RESET register, based on REGR from cells.h.
module GRegr(q , d , mclk , hld, reset );
output q; // 1-bit Q outputs.
input d; // 1-bit D inputs.
input mclk; // Single free-running clock for all registers.
input hld; // Single gate input for all registers.
input reset; // Single gate input for all registers.
wire q;
MflipflopR_1 Greg_r_1(q,d,mclk,hld,reset) ;
endmodule
//----------------------------------------------------------------------------
// 1-bit gated register, based on REG from cells.h.
module GReg1(q , d , mclk , hld);
output q; // 1-bit Q outputs.
input d; // 1-bit D inputs.
input mclk; // Single free-running clock for all registers.
input hld; // Single gate input for all registers.
wire q;
Mflipflop_1 GReg_1_1(q,d,mclk,hld) ;
endmodule
//----------------------------------------------------------------------------
// 2-bit gated register, based on REG from cells.h.
module GReg2(q , d , mclk , hld);
output [1:0] q; // 2-bit Q outputs.
input [1:0] d; // 2-bit D inputs.
input mclk; // Single free-running clock for all registers.
input hld; // Single gate input for all registers.
wire [1:0] q;
Mflipflop_2 GReg_2_2(q,d,mclk,hld) ;
endmodule
//----------------------------------------------------------------------------
// 3-bit gated register, based on REG from cells.h.
module GReg3(q , d , mclk , hld);
output [2:0] q; // 3-bit Q outputs.
input [2:0] d; // 3-bit D inputs.
input mclk; // Single free-running clock for all registers.
input hld; // Single gate input for all registers.
wire [2:0] q;
Mflipflop_3 GReg_3_3(q,d,mclk,hld) ;
endmodule
//----------------------------------------------------------------------------
// 4-bit gated register, based on REG from cells.h.
module GReg4(q , d , mclk , hld);
output [3:0] q; // 4-bit Q outputs.
input [3:0] d; // 4-bit D inputs.
input mclk; // Single free-running clock for all registers.
input hld; // Single gate input for all registers.
wire [3:0] q;
Mflipflop_4 GReg_4_4(q,d,mclk,hld) ;
endmodule
//----------------------------------------------------------------------------
// 5-bit gated register, based on REG from cells.h.
module GReg5(q , d , mclk , hld);
output [4:0] q; // 5-bit Q outputs.
input [4:0] d; // 5-bit D inputs.
input mclk; // Single free-running clock for all registers.
input hld; // Single gate input for all registers.
wire [4:0] q;
Mflipflop_5 GReg_5_5(q,d,mclk,hld) ;
endmodule
//----------------------------------------------------------------------------
// 6-bit gated register, based on REG from cells.h.
module GReg6(q , d , mclk , hld);
output [5:0] q; // 6-bit Q outputs.
input [5:0] d; // 6-bit D inputs.
input mclk; // Single free-running clock for all registers.
input hld; // Single gate input for all registers.
wire [5:0] q;
Mflipflop_6 GReg_6_6(q,d,mclk,hld) ;
endmodule
//----------------------------------------------------------------------------
// 7-bit gated register, based on REG from cells.h.
module GReg7(q , d , mclk , hld);
output [6:0] q; // 7-bit Q outputs.
input [6:0] d; // 7-bit D inputs.
input mclk; // Single free-running clock for all registers.
input hld; // Single gate input for all registers.
wire [6:0] q;
Mflipflop_7 GReg_7_7(q,d,mclk,hld) ;
endmodule
//----------------------------------------------------------------------------
// 8-bit gated register, based on REG from cells.h.
module GReg8(q , d , mclk , hld);
output [7:0] q; // 8-bit Q outputs.
input [7:0] d; // 8-bit D inputs.
input mclk; // Single free-running clock for all registers.
input hld; // Single gate input for all registers.
wire [7:0] q;
Mflipflop_8 GReg_8_8(q,d,mclk,hld) ;
endmodule
//----------------------------------------------------------------------------
// 9-bit gated register, based on REG from cells.h.
module GReg9(q , d , mclk , hld);
output [8:0] q; // 9-bit Q outputs.
input [8:0] d; // 9-bit D inputs.
input mclk; // Single free-running clock for all registers.
input hld; // Single gate input for all registers.
wire [8:0] q;
Mflipflop_9 GReg_9_9(q,d,mclk,hld) ;
endmodule
//----------------------------------------------------------------------------
// 10-bit gated register, based on REG from cells.h.
module GReg10(q , d , mclk , hld);
output [9:0] q; // 10-bit Q outputs.
input [9:0] d; // 10-bit D inputs.
input mclk; // Single free-running clock for all registers.
input hld; // Single gate input for all registers.
wire [9:0] q;
Mflipflop_10 GReg_10_10(q,d,mclk,hld) ;
endmodule
//----------------------------------------------------------------------------
// 11-bit gated register, based on REG from cells.h.
module GReg11(q , d , mclk , hld);
output [10:0] q; // 11-bit Q outputs.
input [10:0] d; // 11-bit D inputs.
input mclk; // Single free-running clock for all registers.
input hld; // Single gate input for all registers.
wire [10:0] q;
Mflipflop_11 GReg_11_11(q,d,mclk,hld) ;
endmodule
//----------------------------------------------------------------------------
// 12-bit gated register, based on REG from cells.h.
module GReg12(q , d , mclk , hld);
output [11:0] q; // 12-bit Q outputs.
input [11:0] d; // 12-bit D inputs.
input mclk; // Single free-running clock for all registers.
input hld; // Single gate input for all registers.
wire [11:0] q;
Mflipflop_12 GReg_12_12(q,d,mclk,hld) ;
endmodule
//----------------------------------------------------------------------------
// 32-bit gated register, based on REG from cells.h.
module GReg32(q , d , mclk , hld);
output [31:0] q; // 32-bit Q outputs.
input [31:0] d; // 32-bit D inputs.
input mclk; // Single free-running clock for all 32 registers.
input hld; // Single gate input for all 32 registers.
wire [31:0] q;
Mflipflop_32 GReg_32_32(q,d,mclk,hld) ;
endmodule
//----------------------------------------------------------------------------
// 1-bit register with sync'd set/reset , based on REG from cells.h.
// The reset input has priority over set input.
module S_sr_ff(q , en, dis, mclk);
output q;
input mclk; // Single free-running clock for all 32 registers.
input en, dis;
wire Gnd; assign Gnd = 1'b0;
wire d;
assign d = ((q | en) & (~dis));
| This page: |
Created: | Thu Aug 19 12:00:19 1999 |
| From: |
../../../sparc_v8/ssparc/memif/rtl/mem_cells.v
|