/******************************************************************************/ 
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/******************************************************************************/ 
// @(#)rl_memif.v	1.47 11/5/93
/****************************************************************************
 * rl_memif.v
 *
 *      Description:
 *              This is the top level module for memory interface.
 *              The MCB, DPC & RFR modules are instantiated in the 
 *              'rl_memif' module.  No logic is uniquely defined in
 *              this module.  Only connections between the different
 *              modules are defined.
 *  
 *
 *              This module is instantiated by the ssparc.v module?
 *              
 *
 *
 *
 ****************************************************************************/


module rl_memif	( b_memdata_out, b_mempar_out, mc_memaddr, mc_ras_l, 
	   			  mc_cas_l, mc_moe_l, mc_mwe_l, simm32_sel, dp_ben, mc_mstb_l, mc_mbsy, 
				  mc_caddr_hld, dp_perr, dp_perr_buf,
				  mc_mdata0, rl_memif_scan_out,
				  mc_refresh, mc_cfb_data, pdm_ready, 
				  s_reply, aen, ab, p_reply_dec, afx_to, prom_p_reply,
               			  mc_memaddr_in, afx_rst_page_vld, am_gnt_l, am_cstb_l, am_read, 
			//	  falcon_exists, 
				  am_wm, mm_sbae_0,

				  
				  b_memdata_in, b_mempar_in, mm_pa_a, mm_pa_b, mm_caddr, 
				  mm_issue_req, mm_issue_req2,  mm_mreq, mm_page, 
				  mc_mdata_en0, 
				  mm_rf_cntl, mm_oddmpar,  mm_parity_en,
				  pcic_afxm_db_oen,
				  mc_mdata_in, ss_reset,
				  ss_clock, 
				  sp_sel,
				  rl_memif_scan_in, ss_scan_mode, 
				  precharge_early_0,
				  precharge_early_1,
				  rfr_clock, rfr_late,
				  mm_2nd_wd, mm_misc2cf, mm_issue_req_early,
				  mm_fb_req, mm_fb_size, mm_fb_page,
				  gclk_1st_phase, p_reply, pcic_p_reply, mm_mem_dbg,
                                  valid_l, cas_cyc, ab_in, am_gnt_l_oen
				);

	output	[63:0]	b_memdata_out;	// Data out to the Data Pads for DRAM.
	output	[1:0]	b_mempar_out;	// Parity out to the Parity pads for DRAM.
    output  [11:00] mc_memaddr;     // Memory address to Out pads for DRAM.
    output  [07:00] mc_ras_l;       // Four RASes to Out pads for DRAM.
    output  [03:00] mc_cas_l;       // Two CASes to Out pads for DRAM.
    output          mc_moe_l;       // The OE to Out pads for DRAM.
    output          mc_mwe_l;       // The WE to Out pads for DRAM.
	output			dp_ben;			// External Tri-enable to IO-pad Control.
    output          mc_mstb_l;      // Data-ready Strobe to MMU.
    output          mc_mbsy;        // Memory logic busy sig to MMU.
    output          mc_caddr_hld;   // Hold low addr bits. To MMU.
	output	[1:0]	dp_perr;	  	// Parity-Error condition bits to MMU.
	output	[1:0]	dp_perr_buf;	  	// Parity-Error buffered version to d$.
//        output  [1:0]   dp_perr_reg;      //Parity-Error condition bits,registered.
//	output			dp_buf0_en;		// Internal Tri-enable control to MMU.
	output	[31:0]	mc_mdata0;	  	// Write Lo-word to internal dat_bus.
//	output	[31:0]	mc_mdata1;	  	// Write Hi-word to internal dat_bus.
	output			rl_memif_scan_out;
	output			mc_refresh;
	output	[63:0]	mc_cfb_data;		// Bypass data to cache fill bus
	output			pdm_ready;
	output		s_reply;
	output			aen;
	output	[14:12]	ab;
	output	[2:0]	p_reply_dec;
	output			afx_to;

// IIe additions : New Falcon interface
        output          valid_l;
        output          cas_cyc;
        output          am_gnt_l_oen;
 
        input   [11:0]  mc_memaddr_in;
        output          am_gnt_l;
        output          afx_rst_page_vld;
        input           am_cstb_l;
        input           am_read;
//        input           falcon_exists;
        input   [1:0]   am_wm;
        input           mm_sbae_0;
        input   [1:0]   prom_p_reply;

	input	[63:0]	b_memdata_in;	// Data in from Data Pads for DRAM.
	input	[1:0]	b_mempar_in;	// Parity in from the Parity pads for DRAM.
    input   [28:12] mm_pa_a;		// Phys-addr 26:12 from MMU.
    input   [02:00] mm_pa_b;		// Phys-addr 02:00 from MMU.
    input   [11:03] mm_caddr;		// Phys-addr 11:03 (latched) from MMU.
    input           mm_issue_req;	// Valid-request from MMU.
    input           mm_issue_req2;	// Valid-request from MMU.
    input   [03:00] mm_mreq;		// Mem cyc-req from MMU.
    input           mm_page;		// Page mode request from MMU.
	input			mc_mdata_en0;	// Tri_enable, Wr Lo_word, from MMU.
//	input			mc_mdata_en1;	// Tri_enable, Wr Hi_word, from MMU.
	input	[3:0]	mm_rf_cntl;		// Refr-rate select from MMU.
	input			mm_oddmpar;	  	// Selects odd/even parity. From MMU.
	input			mm_parity_en;	  	// Selects parity enable. From MMU.
        input  pcic_afxm_db_oen;		//IIep 2.0: dma_rd par chk 
	input	[31:0]	mc_mdata_in;	// In from internal data bus.
    input           ss_reset;		// System Reset.
    input           ss_clock;		// System Clock.
	input 			simm32_sel;		// for double density simm select 
	input	[2:0]		sp_sel;			// Lo-MHz ("0") or Hi-MHz ("1") select pin. and 150Mhz - 200Mhz
	input			ss_scan_mode;
	input			rl_memif_scan_in;
//	input	    mm_wbstben0;	// strobe for 0th word of store double.
//	input	    mm_wbstben1;	// strobe for 1st word of store double.
//    input           mm_write_buffer_sel;		// selcet from MMU for store buffer write.
//    input   [63:32] st_write_hi;		// High bits from store buffer.
    input           precharge_early_0;		// Precharge 1 cycle for non-page access.
    input           precharge_early_1;		// Precharge 1 cycle for non-page access.
//    input           power_down_mode;		// Enters power down except rfr and mcb.
    input           rfr_clock;		// In power_down_mode, this clock is runing.
    input           rfr_late;		// In power_down_mode, this late clock is runing.
    input           mm_misc2cf;		// select to mux data from misc to $ fill.
    input           mm_2nd_wd;		// select to mux d-word from misc to $ fill.
    input           mm_issue_req_early;	// mm_issue_req_early to hold off refresh.
    input           mm_fb_req;	// 
    input  [1:0]    mm_fb_size;	// 
    input      	    mm_fb_page;	// 
    input           gclk_1st_phase;	// 
    input  [1:0]    p_reply;	// 
    input  [1:0]    pcic_p_reply; 	// pcic p_reply
    input  [1:0]    mm_mem_dbg;	// 
    input  [14:12]  ab_in;      //  Upper 3 address bit from the Falcon.





// new partition here:
	wire [31:0] bd_mux_out1;
	wire [31:0] bd_mux_out0;
	wire qaud_sel;
	wire qaud_sel_dwd;
	wire out_hld_2;
	wire out_hld_3;

//	wire rl_memif_major_scan_out;
//	wire rl_memif_major_scan_in;
//	wire rl_memif_minor_scan_out;
//	wire rl_memif_minor_scan_in;
//
//	assign rl_memif_major_scan_in = rl_memif_scan_in;
//	assign rl_memif_minor_scan_in = rl_memif_major_scan_out;
//	assign rl_memif_scan_out = rl_memif_minor_scan_out;

	rl_memif_major memif_major ( b_memdata_out, b_mempar_out, mc_memaddr, mc_ras_l,
                                  mc_cas_l, mc_moe_l, mc_mwe_l, simm32_sel, dp_ben, mc_mstb_l, mc_mbsy,
                                  mc_caddr_hld, dp_perr, dp_perr_buf,
                                  mc_mdata0, rl_memif_scan_out,
                                  mc_refresh, mc_cfb_data, pdm_ready,
                                  s_reply, aen, ab, p_reply_dec, afx_to, prom_p_reply,
				  quad_sel_dwd, quad_sel_dwd_1, quad_sel,
				  out_hld_2, out_hld_3,
		                  mc_memaddr_in, afx_rst_page_vld, am_gnt_l, am_cstb_l, am_read, 
				 // falcon_exists, 
				  am_wm, mm_sbae_0,


 				  b_memdata_in, b_mempar_in, mm_pa_a, mm_pa_b, mm_caddr,
                                  mm_issue_req, mm_issue_req2,  mm_mreq, mm_page,
                                  mc_mdata_en0,
                                  mm_rf_cntl, mm_oddmpar,  mm_parity_en,
				  pcic_afxm_db_oen,
                                  bd_mux_out1, bd_mux_out0, ss_reset, ss_clock, sp_sel,
                                  rl_memif_scan_in, ss_scan_mode,
                                  precharge_early_0,
                                  precharge_early_1,
                                  rfr_clock, rfr_late,
                                  mm_2nd_wd, mm_misc2cf, mm_issue_req_early,
                                  mm_fb_req, mm_fb_size, mm_fb_page,
                                  gclk_1st_phase, p_reply, pcic_p_reply, mm_mem_dbg,
                                  valid_l, cas_cyc, ab_in, am_gnt_l_oen
                                );


        rl_memif_minor   memif_minor(bd_mux_out1, bd_mux_out0, 

					quad_sel_dwd, quad_sel_dwd_1, quad_sel,
					mc_mdata_in, out_hld_2, out_hld_3,
					ss_clock);

// Added spare cells 

        spares  rl_memif_spares ();


endmodule