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/***************************************************************************
****************************************************************************
***
***  Program File:  @(#)special.v
***
****************************************************************************
****************************************************************************/

/*  @(#)special.v	1.2  5/28/92  */
//
// **************************************************************
//  special -- this module detects IEEE multiply special cases and
//		generates the fpm_unfin (unfinished) signal
//
//  Special Cases:
//  1.  rs1_exp is all 0's or all 1's
//  2.  rs2_exp is all 0's or all 1's
//  3.  exp_res_0 <= 0, or exp_res_1 >= 2047  (127 single)
//
// **************************************************************


module special	(
		fpm_unfin,
		rs1_e,
		rs2_e,
		exp_res_0[12:0],
		exp_res_1[12:0],
		fpm_inst
		);

    output fpm_unfin;

    input [10:0] rs1_e;		// 11-bit multiplicand (X) exponent
    input [10:0] rs2_e;		// 11-bit multiplier (Y) exponent
    input [12:0] exp_res_0;	// exponent adder output
    input [12:0] exp_res_1;	// exponent adder output + 1
    input [1:0]  fpm_inst;	// FMULs=00, FMULd=01, FsMULd=10

    wire rs1_udf     = (rs1_e[10:0] == 11'b00000000000) ;
    wire rs1_sgl_ovf = (rs1_e[7:0]  == 8'b11111111) ;
    wire rs1_dbl_ovf = (rs1_e[10:8] == 3'b111) ;
    wire rs1_ovf = rs1_sgl_ovf & (~fpm_inst[0] | rs1_dbl_ovf) ;

    wire rs2_udf     = (rs2_e[10:0] == 11'b00000000000) ;
    wire rs2_sgl_ovf = (rs2_e[7:0]  == 8'b11111111) ;
    wire rs2_dbl_ovf = (rs2_e[10:8] == 3'b111) ;
    wire rs2_ovf = rs2_sgl_ovf & (~fpm_inst[0] | rs2_dbl_ovf) ;

				// (exp_res_0 <= 0)
				// note:  res_udf will trigger when
				// exp_res_0==0x800; this is okay because
				// fpm_unfin will trigger anyway
    wire res_udf = exp_res_0[12] | (exp_res_0[10:0] == 11'b00000000000) ;

				// FMULd or FsMULd
    wire res_dbl = fpm_inst[0] | fpm_inst[1] ;

				// ((exp_res_1 >= 255) || (exp_res_1 >= 2047))
				// note: also triggers on (exp_res_1 < 0), but
				// that's okay
    wire res_sgl_ovf = (exp_res_1[7:0]  == 8'b11111111) ;
    wire res_dbl_ovf = (exp_res_1[10:8] == 3'b111) ;
    wire res_ovf = (exp_res_1[11] & res_dbl)  |
		   (exp_res_1[8]  & ~res_dbl) |
		   (res_sgl_ovf & (~res_dbl | res_dbl_ovf)) ;

    wire fpm_unfin = (rs1_udf | rs1_ovf | rs2_udf | rs2_ovf |
			res_udf | res_ovf) ;

endmodule