/******************************************************************************/
/* */
/* Copyright (c) 1999 Sun Microsystems, Inc. All rights reserved. */
/* */
/* The contents of this file are subject to the current version of the Sun */
/* Community Source License, microSPARCII ("the License"). You may not use */
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/******************************************************************************/
/***************************************************************************
****************************************************************************
***
*** Program File: @(#)fpm_exp.v
***
****************************************************************************
****************************************************************************/
/* @(#)fpm_exp.v 1.4 7/10/92 */
//
// **************************************************************
// fpm_exp -- structural description of exponent portion of floating
// point multiplier.
//
// This datapath generates the result exponent:
// (rs1_e + rs2_e) - 1023 (FMULd)
// (rs1_e + rs2_e) - 127 (FMULs)
// (rs1_e + rs2_e) + 769 (FsMULd)
//
// This datapath also detects special cases and generates the fpm_unfin
// (unfinished) signal.
//
// **************************************************************
module fpm_exp (
fpm_exp_scan_in,
fpm_exp_scan_out,
ss_scan_mode,
fpm_exp,
fpm_unfin,
frac_ovf,
rs1_e,
rs2_e,
fpm_inst,
fpm_start,
fpm_clk
);
//prop CELLCLASS "MODULE"
input fpm_exp_scan_in
;
output fpm_exp_scan_out
;
input ss_scan_mode
;
output [10:0] fpm_exp
; // 11-bit exponent
// Registered output, valid in W stage.
output fpm_unfin
; // Multiplier unfinished signal (special
// case detected)
// Registered output, valid in W stage.
input frac_ovf
; // fraction overflow (fpm_f >= 2.0)
// 52-bit add + 2 gate delays into X3 stage
input [10:0] rs1_e
; // 11-bit operand: multiplicand (X exponent)
// Registered in X1 stage
input [10:0] rs2_e
; // 11-bit operand: multiplier (Y exponent)
// Registered in X1 stage
input [1:0] fpm_inst
; // FMULs=00, FMULd=01, FsMULd=10
// Expected valid same time as fpm_start
input fpm_start
; // go-ahead signal
// Should be active for 1 cycle only.
input fpm_clk
; // single phase master clock
wire [10:0] rs1_e;
wire [10:0] rs2_e;
wire fpm_start;
wire fpm_clk;
wire [1:0] fpm_instX123
; // registered fpm_inst
wire [12:0] rs1_eX12
; // registered rs1 (multiplicand) mantissa
wire [12:0] rs2_eX12
; // registered rs2 (multiplier) mantissa
wire passX1
; // fpm_start asserted in X1
wire passX2
; // fpm_start asserted in X2
wire passX3
; // fpm_start asserted in X3
wire fpm_unfinX1
; // output of special case logic
wire [12:0] exp_res_0
; // final adder output
wire [12:0] exp_res_1
; // final adder output (+1)
wire [10:0] exponent
; // final mux output
ME_TIEOFF t1 (VDD
, GND
) ;
//
// controller
//
ME_FD1 rgstrX1 (.q(passX1),
.d(fpm_start),
.cp(fpm_clk)
);
ME_FD1 rgstrX2 (.q(passX2),
.d(passX1),
.cp(fpm_clk)
);
ME_FD1 rgstrX3 (.q(passX3),
.d(passX2),
.cp(fpm_clk)
);
wire [10:0] opx_e
, opy_e
;
//
// Operand select (single/double) muxes
//
ME_MUX_2B_11 opxMux (fpm_inst[0],
{GND, GND, GND, rs1_e[10:3]},
rs1_e[10:0], // selected when fpm_inst == x1
opx_e[10:0]
);
ME_MUX_2B_11 opyMux (fpm_inst[0],
{GND, GND, GND, rs2_e[10:3]},
rs2_e[10:0], // selected when fpm_inst == x1
opy_e[10:0]
);
//
// stage X1, X2
//
ME_FREGA_1_2 dblReg (
.Q( fpm_instX123[1:0] ),
.D( fpm_inst[1:0] ),
.enable(fpm_start),
.clk(fpm_clk)
);
assign rs1_eX12[12:11] = {GND, GND};
ME_FREGA_1_11 xReg (
.Q( rs1_eX12[10:0] ),
.D( opx_e[10:0] ),
.enable(fpm_start),
.clk(fpm_clk)
);
assign rs2_eX12[12:11] = {GND, GND};
ME_FREGA_1_11 yReg (
.Q( rs2_eX12[10:0] ),
.D( opy_e[10:0] ),
.enable(fpm_start),
.clk(fpm_clk)
);
wire [12:0] const_sum
;
wire [12:0] const_carry
;
expconstadd
cnstAdd (const_sum[12:0], // add exponent bias constant
const_carry[12:0],
rs1_eX12[10:0],
rs2_eX12[10:0],
fpm_instX123[1:0]
);
dual_adder13
expadd (.sum_0( exp_res_0[12:0] ), // (A+B-C)
.sum_1( exp_res_1[12:0] ), // (A+B+1-C)
.x( const_sum[12:0] ),
.y( const_carry[12:0])
);
special fpmSpecial (
fpm_unfinX1,
rs1_eX12[10:0],
rs2_eX12[10:0],
exp_res_0[12:0],
exp_res_1[12:0],
fpm_instX123[1:0]
);
ME_MUX_2B_11 resMux (frac_ovf,
exp_res_0[10:0],
exp_res_1[10:0], // selected when frac_ovf == 1
exponent[10:0]
);
//
// stage X3
//
ME_FREGA_1_11 ZReg (
.Q( fpm_exp[10:0] ),
.D( exponent[10:0] ),
.enable(passX3),
.clk(fpm_clk)
);
ME_FD1E unfinReg (
.q(fpm_unfin),
.d(fpm_unfinX1),
.te(passX3),
.cp(fpm_clk)
);
endmodule
This page: |
Created: | Thu Aug 19 12:03:36 1999 |
| From: |
../../../sparc_v8/ssparc/fpu/fp_fpm/rtl/fpm_exp.v
|