/******************************************************************************/ 
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/* Copyright (c) 1999 Sun Microsystems, Inc. All rights reserved.             */ 
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/***************************************************************************
****************************************************************************
***
***  Program File:  @(#)sticky.v
***
****************************************************************************
****************************************************************************/

//  @(#)sticky.v	1.2  4/9/92
//
// **************************************************************
//  sticky -- 2 pass sticky-bit generator
// **************************************************************


module sticky(sticky, sum, passX1, fpm_clk);

    output sticky;		// sticky output

    input  [27:0] sum;		// sum bits from array
    input  passX1;
    input  fpm_clk;


    wire s28, s28_term;

					// reduction-or or's all bits together
    wire s51 = ( | sum[22:0]) | s28_term ;	// corresponds to OR-ing
						// sum[50:28] and sum[27:0]

    wire s28_in = ( | sum[27:23]) | s51 ;

    assign s28_term = s28 & ~passX1;		// clear s28 before passX2

    ME_FD1 s28_reg (.q(s28),			// valid in passX2
		    .d(s28_in),
		    .cp(fpm_clk)
		   );

    ME_FD1 s51_reg (.q(sticky),			// valid in passX3
		    .d(s51),
		    .cp(fpm_clk)
		   );

endmodule