/******************************************************************************/
/* */
/* Copyright (c) 1999 Sun Microsystems, Inc. All rights reserved. */
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/******************************************************************************/
/***************************************************************************
****************************************************************************
***
*** Program File: @(#)fpm_frac.v
***
****************************************************************************
****************************************************************************/
// @(#)fpm_frac.v 1.5 11/13/92
//
// **************************************************************
// fpm_frac -- structural description of mantissa portion of floating
// point multiplier.
//
// **************************************************************
module fpm_frac (
ss_scan_mode,
fpm_frac_scan_in,
fpm_frac_scan_out,
fpm_frac,
fpm_sign,
fpm_inx,
frac_ovf,
rs1_s,
rs1_m,
rs2_s,
rs2_m,
fpm_inst,
rnd_mode,
fpm_start,
fpm_clk
);
input ss_scan_mode
;
input fpm_frac_scan_in
;
output fpm_frac_scan_out
;
output [51:0] fpm_frac
; // 52-bit fraction (no sign, no implicit).
// Registered output, valid in W stage.
output fpm_sign
; // Product sign bit. Registered output.
output fpm_inx
; // Inexact flag.
// 52-bit add + 4 gate delays into X3 stage
output frac_ovf
; // fraction overflow (fpm_f >= 2.0)
// 52-bit add + 3 gate delays into X3 stage
input rs1_s
; // multiplicand sign
// Registered in X1 stage
input [54:0] rs1_m
; // 55-bit operand: multiplicand (X mantissa)
// Registered in X1 stage
input rs2_s
; // multiplier sign
// Registered in X1 stage
input [54:0] rs2_m
; // 55-bit operand: multiplier (Y mantissa)
// Registered in X1 stage
input [1:0] fpm_inst
; // FMULs=00, FMULd=01, FsMULd=10
// Expected valid same time as fpm_start
input [1:0] rnd_mode
; // rounding mode (same as FSR[31:30])
// Expected valid in X3 stage
input fpm_start
; // go-ahead signal
// Should be active for 1 cycle only.
input fpm_clk
; // single phase master clock
wire rs1_s;
wire [54:0] rs1_m;
wire rs2_s;
wire [54:0] rs2_m;
wire [1:0] rnd_mode;
wire fpm_start;
wire fpm_clk;
wire [52:0] rs1_mX12
; // registered rs1 (multiplicand) mantissa
wire [52:0] rs2_mX12
; // registered rs2 (multiplier) mantissa
wire rs1_sX12
; // registered rs1 sign
wire rs2_sX12
; // registered rs1 sign
wire [79:0] sum
; // half array redundant sum
wire [79:1] carry
; // half array redundant carry
wire [79:23] sumX12
; // registered redundant sum
wire [79:23] carryX12
; // registered redundant carry
wire [105:51] sumX3
; // recoded sum
wire [105:52] carryX3
; // recoded carry
wire passX1
; // fpm_start asserted in X1
wire passX2
; // fpm_start asserted in X2
wire passX3
; // fpm_start asserted in X3
wire signX3
; // registered mantissa sign
wire stickyX3
; // registered sticky bit
wire c51X3
; // registered carry into result 51
wire [52:0] mantissa
; // final adder output
ME_TIEOFF t1 (VDD
, GND
) ;
assign fpm_sign = signX3 ;
//
// controller
//
ME_FD1 rgstrX1 (
.q(passX1),
.d(fpm_start),
.cp(fpm_clk)
);
ME_FD1 rgstrX2 (
.q(passX2),
.d(passX1),
.cp(fpm_clk)
);
ME_FD1 rgstrX3 (
.q(passX3),
.d(passX2),
.cp(fpm_clk)
);
wire [52:0] opx_m
, opy_m
;
//
// Operand select (single/double) muxes
//
// single precision operand X has 15 trailing pad zeros
ME_MUX3_53 opxmux (
opx_m[52:0],
fpm_inst[0], fpm_inst[1],
{GND, GND, GND, GND, GND, GND, GND, GND, // FMULs
GND, GND, GND, GND, GND, GND,
VDD, rs1_m[54:32],
GND, GND, GND, GND, GND, GND, GND, GND,
GND, GND, GND, GND, GND, GND, GND},
{VDD, rs1_m[51:0]}, // FMULd
{VDD, rs1_m[54:32], GND, GND, GND, GND, // FsMULd
GND, GND, GND, GND, GND, GND, GND, GND,
GND, GND, GND, GND, GND, GND, GND, GND,
GND, GND, GND, GND, GND, GND, GND, GND,
GND}
);
// single precision operand Y has 14 trailing pad zeros
// opymux_lo muxes in the high 25-bits for passX2 in array
ME_MUX3_25 opymux_hi ( opy_m[52:28],
fpm_inst[0], fpm_inst[1],
{GND, GND, GND, GND, GND, GND, GND, GND, // FMULs
GND, GND, GND, GND, GND, GND, GND,
VDD, rs2_m[54:46] },
{VDD, rs2_m[51:28] }, // FMULd
{VDD, rs2_m[54:32], GND } // FsMULd
);
wire [1:0] opymux_lo_ctl
;
assign opymux_lo_ctl[0] = fpm_inst[0] | passX1 ;
assign opymux_lo_ctl[1] = fpm_inst[1] | passX1 ;
ME_MUX41H28 opymux_lo ( opy_m[27:0],
{rs2_m[45:32], // FMULs
GND, GND, GND, GND, GND, GND, GND, GND,
GND, GND, GND, GND, GND, GND },
rs2_m[27:0], // FMULd
{GND, GND, GND, GND, GND, GND, GND, GND, // FsMULd
GND, GND, GND, GND, GND, GND, GND, GND,
GND, GND, GND, GND, GND, GND, GND, GND,
GND, GND, GND, GND },
{GND, GND, GND, rs2_mX12[52:28] }, // passX2
opymux_lo_ctl[0], opymux_lo_ctl[1]
);
// FMULd or FsMULd
wire res_dbl
= fpm_inst[0] | fpm_inst[1] ;
//
// stage X1, X2
//
ME_FD1E dblReg (
.q(res_dblX123
),
.d(res_dbl),
.te(fpm_start),
.cp(fpm_clk)
);
ME_FREGA_1_54 xReg (
.Q( {rs1_sX12, rs1_mX12[52:0]} ),
.D( {rs1_s, opx_m[52:0]} ),
.enable(fpm_start),
.clk(fpm_clk)
);
ME_FREGA_1_26 yReg_hi ( // yReg[53:28]
.Q( {rs2_sX12, rs2_mX12[52:28]} ),
.D( {rs2_s, opy_m[52:28]} ),
.enable(fpm_start),
.clk(fpm_clk)
);
wire yReg_lo_en
= fpm_start | passX1 ;
ME_FREGA_1_28 yReg_lo ( // yReg[27:0]
.Q( rs2_mX12[27:0] ),
.D( opy_m[27:0] ),
.enable(yReg_lo_en),
.clk(fpm_clk)
);
array array (
sum[79:0],
carry[79:1],
rs1_mX12[52:0],
rs2_mX12[27:0],
passX2,
sumX12[79:28],
carryX12[79:28]
);
ME_FDREG_1_57 sumReg (
.Q( sumX12[79:23] ),
.D( sum[79:23] ),
.clk(fpm_clk)
);
ME_FDREG_1_57 carryReg (
.Q( carryX12[79:23] ),
.D( carry[79:23] ),
.clk(fpm_clk)
);
//
// sign generation
//
sign signLogic (
signX3,
rs1_sX12,
rs2_sX12,
passX2,
fpm_clk
);
//
// sticky bit
//
sticky stickyLogic (
stickyX3,
sum[27:0],
passX1,
fpm_clk
);
//
// carry 51
//
carry51 carry51Logic (
c51X3,
sum[27:0],
carry[27:1],
passX1,
fpm_clk
);
//
// stage X3
//
//
// recode using half-adders
//
half_adder55 half_adder55 (
sumX3[105:51],
carryX3[105:52],
sumX12[77:23],
carryX12[77:23]
);
final_adder
final_adder (
mantissa[52:0],
man_inx
,
frac_ovf, // fraction overflow (mantissa >= 2.0)
sumX3[105:51],
carryX3[105:52],
rnd_mode[1:0],
signX3,
stickyX3,
c51X3,
res_dblX123
);
ME_FREGA_1_52 ZReg (
.Q( fpm_frac[51:0] ),
.D( mantissa[51:0] ), // mantissa[52] is the implicit 1
.enable(passX3),
.clk(fpm_clk)
);
ME_FD1E inxReg ( // register the inexact status bit
.q(fpm_inx),
.d(man_inx),
.te(passX3),
.cp(fpm_clk)
);
endmodule
This page: |
Created: | Thu Aug 19 12:00:33 1999 |
| From: |
../../../sparc_v8/ssparc/fpu/fp_fpm/rtl/fpm_frac.v
|