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Xilinx Answer #4153 : Orcad Express: DRC check gives error on PULLUP and PULLDOWN components
Xilinx Answer #4144 : Orcad Express: Using Xilinx Alliance Series with Express
Xilinx Answer #4142 : Orcad: Adding third-party Xilinx cores to an Express project
Xilinx Answer #4140 : Orcad, XNFmerge, XMAKE: Failed to find user defined subhierarchy
Xilinx Answer #4138 : Orcad Capture: Recommended design flow with Capture v7.10 and Xilinx M1
Xilinx Answer #4124 : Orcad Simulate: Error: "Cannot create file..." occurs when converting XNF to VHDL
Xilinx Answer #4121 : Orcad simulation: "Translation failed" when using "Convert XNF to VHDL"
Xilinx Answer #4119 : Orcad Express: Timed simulation for Xilinx M1 does not include global reset by default
Xilinx Answer #1639 : OrCAD Capture 7.0: design rule check gives warning message:[DRC0014] for BUFT components
Xilinx Answer #1426 : Orcad VST all outputs are undefined
Xilinx Answer #865 : How to contact OrCAD technical support: hotline, bbs numbers