CPLD Applications 

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XC9500XL XC9500 CoolRunner Tutorials

Configuration Solutions Programmer Solutions XCELL Articles

XC9500XL

Application Notes	Ver.	Date	Size
XAPP144: Designing CPLD Multi-voltage Systems	1.3	03/00	60 KB
XAPP141: In-System Programming Times for XC9500XL	1.0	4/99	18 KB
XAPP115: Planning for High Speed XC9500XL Designs	1.0	9/98	110 KB
XAPP114: Understanding XC9500XL CPLD Power	1.1	1/99	90 KB
XAPP112: Designing With XC9500XL CPLDs	1.1	1/99	160 KB
XAPP111: Using the XC9500XL Timing Model	1.2	1/99	100 KB
Application Brief	Ver.	Date	Size
XBRF017: XC9500XL Versus MAX 7000A Architecture Comparison	1.1	9/98	60 KB

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XC9500

Application Notes	Ver.	Date	Size
XAPP137: Configuring Virtex FPGAs from Parallel EPROMs with a CPLD	1.0	3/99	90 KB
XAPP113: Faster Erase Times for XC95216 and XC95108 Devices on HP 3070 Series Testers	1.0	7/98	30 KB
XAPP110: XC9500 CPLD Power Sequencing	1.0	1/98	30 KB
XAPP109: Hints, Tips and Tricks for using XABEL with Xilinx M1.5 Design and Implementation Tools	2.0	10/98	80 KB
XAPP105: A CPLD VHDL Introduction	1.0	1/98	60 KB
XAPP104: A Quick JTAG ISP Checklist	1.1	1/99	20 KB
XAPP103: The Tagalyzer - A JTAG Boundary Scan Debug Tool	1.0	1/98	130 KB
XAPP102: XC9500 Remote Field Upgrade Associated PC and UNIX design files	1.0	1/98	80 KB
XAPP079: Configuring Xilinx FPGAs Using an XC9500 CPLD and Parallel PROM	1.1	7/00	100KB
XAPP078: XC9536 ISP Demo Board Johnson Shift Counter VHDL Code Johnson Shift Counter ABEL Code VHDL Design Files	1.0	4/97	41 KB
XAPP076: Embedded Instrumentation Using XC9500 CPLDs	1.0	1/97	39 KB
XAPP074: Pin Preassigning with XC9500 CPLDs	1.3	6/98	50 KB
XAPP073: Designing with XC9500 CPLDs	1.3	1/98	70 KB
XAPP071: Using the XC9500 Timing Model	1.0	1/97	47 KB
XAPP070: Using In-System Programmability in Boundary-Scan Systems	1.1	7/97	42 KB
XAPP069: Using the XC9500 JTAG Boundary-Scan Interface	2.0	2/98	122 KB
XAPP068: In-System Programming Times	1.2	4/98	13 KB
XAPP067: Using Serial Vector Format Files to Program XC9500 Devices In-System on Automatic Test Equipment and Third Party Tools	1.1	7/97	40 KB
XAPP058: Xilinx In-System Programming Using an Embedded Microcontroller Associated files are available for PC, Solaris, and HP(files updated 6/99)	2.0	6/99	300 KB

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CoolRunner

Application Notes	Ver.	Date	Size
XAPP352: Utilizing a User Constraint File for CoolRunner CPLDs	1.0	11/00	100 KB
XAPP351: The CoolRunner CPLD IRL Demo	1.0	11/00	500 KB
XAPP350: Implementing HDL with WebPACK ECS Schematic Editor	1.0	12/00	180 KB
XAPP349: CoolRunner CPLD 8051 Microcontroller Interface	1.0	12/00	104 KB
XAPP348: CoolRunner XPLA3 Serial Peripheral Interface Master	1.0	11/00	200 KB
XAPP346: Low Power Tips for CoolRunner Design	1.0	10/00	280 KB
XAPP343: In System Programing of XPLA3 Devices	1.0	8/00	30 KB
XAPP341: UARTs in Xilinx CPLDs	1.2	11/00	35 KB
XAPP339: Manchester Encoder-Decoder for Xilinx CPLDs	1.1	4/00	40 KB
XAPP338: Using Xilinx WebPACK and ModelTech ModelSim Xilinx Edition (MXE)	2.0	10/00	3 MB
XAPP336: Design of a 16b/20b Encoder/Decoder Using a CoolRunner CPLD	1.0	7/00	270 KB
XAPP335: Macrocell Configurations in CoolRunner XPLA3 CPLDs	1.0	4/00	100 KB
XAPP334: Utilizing XPLA3 Universal Control Terms	1.0	1/00	60 KB
XAPP333: CoolRunner XPLA3 I2C Bus Controller Implementation	1.5	11/00	170KB
XAPP332: PinLocking in CoolRunner XPLA3 CPLDs	1.0	1/00	80 KB
XAPP331: Reclaiming XPLA1 ISP with VPP Bulk Erase	1.1	10/00	50 KB
XAPP330: XPLA1 Programming Times	1.1	10/00	30 KB
XAPP329: Understanding True CMOS Outputs	1.1	10/00	70 KB
XAPP328: Design of a MP3 Portable Player using a CoolRunner CPLD	1.2	3/00	400 KB
XAPP326: Simplified "In-System Programming" for Embedded Systems Using CoolRunner Devices	1.1	8/00	60 KB
XAPP316: Xilinx Project Navigator XST - XPLA Professional Design  Flow for CoolRunner CPLDs	1.0	9/99	170 KB
XAPP312: Differences In ABEL and PHDL	1.1	10/00	70 KB
XAPP311: Five Volt Tolerance and PCI	1.2	10/00	60 KB
XAPP310: Power Up Reset Characteristics of CoolRunner CPLDs	1.1	2/00	30 KB
XAPP307: Terminating Unused I/O Pins in Xilinx CoolRunner CPLDs	1.3	10/00	30 KB
XAPP302: Metastability Characteristics for CoolRunner CPLDs	1.2	10/00	20 KB
XAPP300: CoolRunner In-System programming (ISP)	1.2	10/00	150 KB
White Paper
WP119: Fast Zero Power Technology	1.0	8/00	50 KB
WP122: Using the CoolRunner XPLA3 Timing Model	1.0	9/00	100 KB
WP108: CoolRunner XPLA3 Clocking Options	1.0	9/00	60 KB
WP105: CoolRunner XPLA3 Architecture Overview	1.0	1/00	200 KB
WP101: The XPLA1 Family Architecture	1.2	10/00	140 KB
Other Links
Users Guide for CoolRunner XPLA3 Development Kit	1.1	7/00	1 MB
Users Manual for XPLA Professional
Schematic Capture Library

Tutorials

Title	Size
Exemplar/ModelSim Tutorial for CPLDs	300 KB
Mentor Schematic Design Tutorial	1 MB
OrCAD/ModelSim Tutorial for CPLDs	200 KB
Synopsys Design Compiler/FPGA Compiler/ModelSim Tutorial for CPLDs	200 KB
Synplify/ModelSim Tutorial for CPLDs	200 KB
Workstation Flow for Xilinx CoolRunner CPLDs	50 KB
Download associated PC design files for VHDL and Verilog

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XCELL Articles

Title	Issue
Xilinx WebPACK Software Now Includes ModelSim	Q3'00
New WebPACK Integrated Synthesis Environment (ISE)	Q3'00
Low Power CoolRunner CPLDs	Q3'00
CoolRunner CPLDs - Your Best Choice for Battery Operation	Q3'00
Fast Zero Power (FZP) Technology	Q2'00
XPLA3 Development Kit	Q2'00
The New XPLA3 CPLD Family - The Best CoolRunner Family Yet	Q1'00