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Module 1:
(85 KB) Introduction and Overview
v1.0 (01/31/02)
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Summary of Features
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General Description
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Architecture
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IP Core and Reference Support
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Device/Package
Combinations and Maximum I/O
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Ordering Information
Module 2:
(505 KB) Functional Description v1.0
(01/31/02)
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Functional Description: Rocket I/OTM Multi-Gigabit Transceiver
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Functional Description: Processor Block
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Functional Description: PowerPCTM 405 Core
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Functional Description: FPGA
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Input/Output Blocks (IOBs)
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Digitally Controlled
Impedance (DCI)
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Configurable Logic
Blocks (CLBs)
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3-State Buffers
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CLB/Slice Configurations
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18-Kb Block SelectRAM
Resources
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18-Bit x 18-Bit
Multipliers
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Global Clock Multiplexer
Buffers
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Digital Clock Manager
(DCM)
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Routing
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Configuration
Module 3:
(235 KB) DC and Switching Characteristics v1.0
(01/31/02)
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Electrical Characteristics
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Performance Characteristics
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Switching Characteristics
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Pin-to-Pin Output
Parameter Guidelines
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Pin-to-Pin Input
Parameter Guidelines
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DCM Timing Parameters
Module 4: (880 KB) Pinout Tables v1.0 (01/31/02)
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Pin Definitions
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Pinout Tables
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FG256
Wire-Bond Fine-Pitch
BGA Package
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FG456
Wire-Bond Fine-Pitch
BGA Package
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FF672
Flip-Chip Fine-Pitch
BGA Package
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FF896 Flip-Chip
Fine-Pitch BGA Package
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FF1152 Flip-Chip
Fine-Pitch BGA Package
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FF1517 Flip-Chip
Fine-Pitch BGA Package
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BF957 Flip-Chip
BGA Package
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