Xilinx Solution Summary
The Internet boom has created the need for faster and faster systems. Microprocessor
speeds are already surpassing 500MHz, but static-memory subsystems including
double data rate (DDR) are hard-pressed to keep pace. Quad Data Rate (QDR)
SRAMs resolve the bandwidth limitation of existing memory solutions, and
provide a high-performance architecture that can be used to provide data
throughputs of 11.592 Gbits/s, this is four times the performance of current
SRAM solutions.
The QDR SRAM architecture, pioneered by the QDR Consortium, consisting
of Cypress Semiconductor, IDT and Micron Technology, provides dedicated
input and output ports that independently operate at double data rate (DDR).
This results in four data transfers per clock cycle and overcomes bus contention
issues. The QDR SRAM I/Os use HSTL signaling, this provides an easy migration
path for future lower voltage levels.
The Spartan-II FPGA, with its unique and extensive features provides
the industry's first memory controller solution for interface with QDR
SRAMs. Moreover, Xilinx provides FREE VHDL source code for implementing
the QDR SRAM memory controller in the low cost Spartan-II FPGA.
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Click here to register for immediate access
to the 'FREE' VHDL source code for the QDR SRAM memory controller. |