| A thru H |
Definition of Terms 
|
| Access Time |
The time it takes to get data into and out of a memory device. |
| Address |
A number that represents a location in the memory. Usually shown in
a hexadecimal value for memory or storage. |
| Architecture |
A general term for describing the design and look of a electronic component;
can either describe hardware or software. |
| Data Width |
Total number of bits/bytes of data that can be accessed (read or written)
simultaneously. |
| DDR |
Double Data Rate. This memory transfers data on both edges of the clock. |
| DRAM |
(Dynamic Random Access Memory) memory that consists of small capacitors
for each bit of memory. Since capacitors do not hold a charge indefinitely,
DRAM must be constantly refreshed to avoid losing its contents. Also, the
process of reading the contents of the memory are destructive, meaning
extra time must be spent restoring the contents of memory addresses which
are accessed, so DRAM is slower than SDRAM |
| MHz |
MegaHertz. A million cycles per second. |
| Memory Controller |
An ASIC or FPGA which interfaces with a memory and enables data transfer. |
| I thru Z |
|
| NoBL SRAM |
No Bus Latency SRAM |
| PBSRAM |
PBSRAM stands for Pipeline Burst SRAM.
The PBSRAM devices have input and output registers for data, which are
not incorporated into the flow-through device. This allows the pipelined
device to operate with a much faster cycle time than the flow-through version. |
| QDR |
QDR stands for Quad Data Rate.
QDR uses two ports to independently run at Double Data Rate, the net result
is four data items per clock cycle, or Quad Data Rate. |
| RAM |
Random Access Memory is a
device that is able to store and retrieve data in any random sequence or
location. |
| Random access |
Reading locations directly without having to read in a particular sequence. |
| SRAM |
(Static Random Access Memory) SRAM consists of one flip-flop per bit
of memory. Unlike DRAMs, static RAM retains its contents as long as power
is applied. Because there is no need to refresh the contents of memory
addresses which are read, SRAM is faster than DRAM, but it is more expensive
and typically is available in much smaller sizes than DRAM because each
bit occupies more space on the chip. |
| ZBT |
Zero Bus Turnaround (ZBT)
is a synchronous SRAM architecture optimized for networking and telecommunications
applications. It can increase the internal bandwidth of a switch fabric
when compared to standard SyncBurst SRAM. ZBT SRAMs became the de facto
industry standard for these applications when they were introduced, much
like Synchronous Burst SRAMs are the industry standard in the PC cache
market.
The ZBT architecture is optimized for switching and other applications
with highly random READs and WRITEs. ZBT SRAMs eliminate all idle cycles
when turning the data bus around from a WRITE operation to a READ operation
(or vice versa). This feature results in dramatic performance improvements
in systems that have such traffic patterns, i.e., frequent and random read
and write access to the SRAM. |
