| FOR IMMEDIATE RELEASE
NEW XILINX SELECTLINKTM
TECHNOLOGY
Web-based tool automatically generates communication
SAN JOSE, Calif., February 7, 2000—Xilinx, Inc. (NASDAQ:XLNX) today announced the availability of its new SelectLink technology that enables designers to create very high speed communications channels between any two Virtex, Virtex-E and Spartan-II FPGAs. The Web-based tool automatically generates Verilog source code and test benches for the fast interchip data channel. SelectLink technology supports an aggregate bandwidth of up to 80 Gigabits per second (Gbps) using multiple I/O pins. "SelectLink technology provides a straightforward and fast method for transferring data between XilinxÒ FPGA devices," said Bruce Weyer, senior director of marketing for the High End FPGA Business Unit at Xilinx. "This tool is simple to use, reduces time to market, and offers our customers a solution for addressing high bandwidth design challenges." SelectLink technology communications channels use standard features of the advanced Xilinx FPGA families such as delay lock loops (DLLs), block RAM, and programmable SelectI/OTM and SelectI/O+TM technologies. SelectLink technology can be used to create a system that delivers throughput of more than 311 Megabits per second (Mbps) per pin for bus widths up to 256 pins. This technology uses proven pre-engineered designs such as Double Data Rate (DDR), clock forwarding, FIFO, and others to help system designers reduce time to market. The web-based SelectLink tool allows logic designers anywhere to instantly create customized Verilog source code using their specific internal and external data buses and FIFO resources. The tool generates in seconds Verilog code and test benches that easily can be integrated into the rest of the system design. The SelectLink technology consists of two main modules. The transmitter module creates a data-width conversion FIFO that has different read and write buses with different widths. This provides an efficient way to funnel data from an internal bus to a narrower external bus. The receiver module reverses the funneling and data rate conversions performed by the transmitter module and performs necessary shifting of data to align it with the signal clock. A SelectLink communications channel can be used with any of the 20 programmable I/O standards supported by the exclusive Virtex-E Select I/O+ technology. For example, for a chip-to-chip interface, designers can use high speed, single ended standards such as SSTL or HSTL. For a board-to-board interface, designers can use differential I/Os such as LVDS, busLVDS or LVPECL. The SelectLink technology tool is accessible from the Xilinx Web site at www.xilinx.com/applications/slcv/selectlink.htm. A complete technical explanation is also available from the Web at www.xilinx.com/products/virtex/techtopic/selectlink.htm. Xilinx is the leading innovator of complete programmable logic solutions, including advanced integrated circuits, software design tools, predefined system functions delivered as cores, and unparalleled field engineering support. Founded in 1984 and headquartered in San Jose, Calif., Xilinx invented the field programmable gate array (FPGA) and fulfills more than half of the world demand for these devices today. Xilinx solutions enable customers to reduce significantly the time required to develop products for the computer, peripheral, telecommunications, networking, industrial control, instrumentation, high-reliability/military, and consumer markets. For more information, visit the Xilinx web site at www.xilinx.com. —30— #0012
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