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Model Technology (MTI) and 
Xilinx Alliance and Foundation Series
Xilinx has established a long standing partnership with Model Technology Incorporated (MTI), a wholly owned subsidiary of Mentor Graphics Corporation, the industry's leading supplier of HDL simulation tools. Model Technology provides Xilinx FPGA and CPLD designers with the latest in simulation technology, regardless of the language (VHDL, Verilog, or mixed HDL) or platform (Unix, Windows, or Linux) that the designer uses.

Now, Xilinx and Model Technology have teamed up to deliver the ModelSim Xilinx Edition (XE) VHDL / Verilog Simulator to Xilinx customers. ModelSim XE is a complete HDL simulation environment optimized for Xilinx, enabling designers to verify source code and functional and timing models of their design using a common "self checking" testbench. A free XE-Starter, included on the CD, familiarizes the user with the ModelSim simulator. 
 

Model Technology in the Xilinx Design Flow
Application Support 
Technical Support Contacts
Model Technology in the Xilinx Design Flow
Model Technology supports all Xilinx devices (FPGA and CPLD). To assure that all Xilinx devices are supported, Xilinx has complied to the following standards and supplied UNISIM/SIMPRIM simulation model support in all of its software products. 
 
Description Version
VHDL Language IEEE-STD-1076-87
Verilog Language IEEE-STD-1364-95
VITAL Modeling Standard IEEE-STD-1076.4-95
Standard Delay Format (SDF) 2.1
Std_logic Data Type IEEE-STD-1164-93


To give the designer a high level of simulation accuracy, Model Technology's ModelSim simulator can be used at three different stages in the Xilinx design flow (see diagram below): 

1. Register Transfer Level (RTL) simulation, which may include the following 

  • Instantiated Xilinx UNISIM library components 
  • Behavioral models created by Xilinx CORE Generator
  • LogiBLOX modules 
    • 2. Post-synthesis (pre-NGDBuild) functional simulation with one of the following 
    (Exemplar LeonardoSpectrum support only at this time) 
  • Gate level UNISIM library components 
  • LogiBLOX modules 
  • CORE Generator behavioral models 
    • 3. Post-route back-annotated timing simulation with the following 
  • Xilinx SIMPRIM library components 
  • Standard Delay Format (SDF) file 


    • The designer uses either VHDL or Verilog for design specification, compiles the Xilinx UNISIM/SIMPRIM libraries using ModelSim, and then, synthesizes the design. The EDIF (or XNF) netlist generated from synthesis is directly accepted into the Xilinx Alliance Series or Foundation Series products.

    After placement and mapping, the Xilinx tools generate a VHDL or Verilog netlist with an SDF file for back-annotating timing delays. A test bench template is automatically generated with the -tb option available in the Xilinx tools. The designer fills the template with vectors and verifies the design with ModelSim. 

    Compiling Libraries

    Application Support
    Xilinx supports ModelSim with the following Application Notes and other application material.
    to view the  files below.

    Application Notes
    * Model Technology application notes

    Other Application Material


    Technical Support Contacts
    For Xilinx supplied tools, interfaces, and libraries, 
    see the following.    		 For Model Technology supplied products, 
    see the following.
    Xilinx Technical SupportInternet Link MTI Technical SupportInternet Link
    Xilinx Answers Database (online 24/7) MTI Support Page for XilinxInternet Link
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    Model Technology and ModelSim are trademarks/registered trademarks of Mentor Graphics Corporation.