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Foundation
Series v2.1i Software
A Complete, Ready
to Use
Programmable Logic
Design Environment
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The
Foundation Series software has been designed to enable both new and experienced
programmable logic designers to achieve handcrafted results automatically,
through push-button design flows. You are assured of success on each
and every design because Foundation Series gives you the advanced tools
and technology you need, and you are backed by our well staffed, highly
skilled, software applications support team.
HDL
Design Made Simple
The Foundation Series includes a comprehensive
set of HDL design tools that support both VHDL and Verilog. Graphical
entry capabilities are provided in a complete, mixed level design environment,
featuring:
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HDL Editor - Provides extensive color
coded editing and searching capabilities with integrated syntax checking |
Language Assistant / Design Wizard - Speeds
design entry by managing the Xilinx supplied library of commonly used language
constructs and logic modules, as well as user created libraries |
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State Editor - Enables fast, intuitive,
graphical entry of both simple and complex state machines. |
HDL Synthesis and Optimization is performed using
an embedded version of Synopsys FPGA Express technology. Coding errors
found during compilation are highlighted directly in the source code, to
simplify your debugging. All shipments of Foundation Series also include
free evaluation versions of ModelSim PE HDL Simulation products, enabling
Xilinx customers to test drive source code debugging tools from Model Technology
Inc.
Advanced
Synthesis Technology
Vista - FPGA Express Schematic Viewer |
The Foundation Series Express product configurations
incorporate world class EDA technology developed by our strategic partners.
New in this release is the latest FPGA Express synthesis engine from Synopsys
(v3.2), which brings unprecedented levels of design performance, and productivity
for your VHDL and Verilog HDL designs. Foundation Series automated design
flows embed the FPGA Express technology, dramatically improving designer
productivity for both mixed-level and all HDL design flows. |
Push-button,
Mixed-level Design Environment
All of the advanced technology within the Foundation
Series works seamlessly together. For example, you can embed VHDL and Verilog
components into a top level schematic, and then simulate the entire design.
With the push of a button, all of the design source files are compiled
into the Xilinx Programmable Logic Device that you specified - meeting
the timing specification you supplied using the Foundation Series Constraints
Editor. |
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So while you have complete control over
every aspect of the design entry, synthesis and implementation process,
you also can apply intuitive, push-button design techniques that simplify
the completion of your design.
Embedded
CORE Generator Simplifying IP Integration
The Xilinx CORE Generator, now embedded in the Alliance
and Foundation Series v2.1i software, simplifies the integration of intellectual
property into your design by providing drop-in access to flexible, high
performance FPGA-based cores. |
The CORE Generator tool includes an intuitive navigation tree for searching
and selecting cores from Xilinx or Xilinx AllianceCORE Partners.
Additionally, Xilinx LogiCORE modules utilize Smart-IP technology which
ensures that Xilinx Cores use the architectural advantages of Xilinx FPGAs
resulting in high performance, predictable, repeatable, and flexible core-based
designs. |
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The
Industry's Most Advanced Implementation Tools
The Foundation Series also includes Xilinx' latest
implementation tools, seamlessly
integrated to help you create the most
efficient and compact designs that operate at the highest possible speed.
These features include
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Timing Driven Place and Route - Allows you
to specify your timing requirements for critical paths. This feature often
gives 30-40% performance improvements when speed is critical; you no longer
need to manually fine-tune your design.
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Static Timing Analysis - Shortens your design
process by providing an evaluation of your timing at various points in
the implementation process, allowing you to make changes immediately.
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Flow Engine - Automates and simplifies the
implementation process. Using a simple graphical interface, you can
monitor and control all aspects of your design implementation.
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Simulation - Provides design verification
before and after implementation, thus reducing the number of design iterations
required to meet design specifications.
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Incremental Design Capability - Reduces your
overall design cycle by allowing you to re-use previous iterations of your
design. This is very helpful for evaluating design alterations.
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Hierarchical Timing Analysis - The Interactive
Timing Analyzer has received a variety of dramatic improvements to its
User interface, including hierarchical reporting of timing analysis results.
This feature simplifies the process of navigation through the rich set
of timing information Xilinx provides on your design.
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In-System Debugging with Probe - Provides real time access to any
internal signal for system level debugging. It does not require modifications
to the source design or design recompilation. See Probe
to learn its benefits and how to use it.
Foundation
Series Product Configurations
Foundation Series software supports a variety of devices and is the
first to support the industry's first two million gate FPGA. Foundation
Series software is available in four product configurations; each licensed
in accordance with the Annual License
Program. The devices supported in each configuration is outlined below.
Device Support
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v2.1i Foundation Base and Base Express
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CPLDs |
XC9500/XL/XV |
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v2.1i Foundation Express (Standard)
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CPLDs |
XC9500/XL/XV |
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v 2.1i Foundation Elite (Available Sept.
1999!)
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CPLDs |
XC9500/XL/XV |
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FPGAs |
Virtex XCV50 |
XC4000E/X
(Up to XC4010E/X)* |
All Spartan/XL |
All XC3x00A/L |
XC5200
(Up to XC5210) |
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FPGAs |
Virtex
(Up to XCV1000E) |
All XC4000E/X |
All Spartan/XL |
All XC5200 |
All XC3x00A/L |
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FPGAs |
All Virtex/E |
All XC4000E/X |
All Spartan/XL |
All XC5200 |
All XC3x00A/L |
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*Note:The XC4013L and XC4013XL devices are supported
in the Foundation Series Base System
All Foundation Series product configurations other than Foundation Base
embed FPGA Express synthesis technology from Synopsys providing unprecedented
levels of design performance, and productivity for your VHDL and Verilog
HDL designs. Foundation Express and Foundation Elite also
include the FPGA Express graphical constraints editor, Time Tracker and
Vista GUIs.
Platform
and System Requirements
Platform Support
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IBM PC or Compatible
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Win95/Win98
(Chinese, Korean, US, Japanese)
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Windows NT 4.0
(US, Japanese)
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NEC98
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120 MHz Pentium processor
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389 MB of hard disk space
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48 MB of RAM
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64 MB of Virtual Memory
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4x CD-ROM drive
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The memory requirements for both RAM and
hard disk space will vary depending on your target device family and size
as well as the unique characteristics of your design. For detailed
listings of the memory requirements specific to your installation, please
reference the Foundation Series 2.1i Release Notes and Installation Guide
on WebLINX. |
Feature
Summary
The Foundation Series supports the full line
of Xilinx FPGAs and CPLDs including our XC3000, XC4000E/X/XL/XV, XC5200,
XC9500,Spartan/XL and Virtex families. Also included are synthesis tools
for ABEL; interfaces to EDIF, VHDL, and Verilog; and the most efficient
HDL design tools in the industry. The table below lists the Foundation
Series features.
Features |
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Foundation
Series Part Numbers |
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FND-BAS
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FND-BSX
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FND-EXP
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FND-ELI
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Synthesis Constraints Editor
and Timing Analyzer |
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Synopsys FPGA Express Synthesis
(VHDL and Verilog synthesis) |
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Web Enabled Design Features |
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ABEL Synthesis |
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HDL Design Tools
HDL Wizard, Context Sensitive HDL Editor, Graphical State
Editor, and Language Assistant |
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Schematic Editor |
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LogiBLOX Module Generator |
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Xilinx CORE Generator System |
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Simulator (Functional and Timing) |
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HDL Simulation Libraries
(UniSim and Simprim) |
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EDIF, VHDL (VITAL), and Verilog
Back Annotation |
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Implementation Tools
Design Manager, Flow Engine, Timing Analyzer, Hardware
Debugger, JTAG Programmer, PROM File Formatter, Graphical Constraint Editor,
Graphical Floorplanner |
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CPLD Devices Supported
XC9500 & XC9500XL (All) |
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FPGA (Base System Device Support)
XC3x00A/L (All)
XC4000E/X (Up to XC4010E/X)*
XC5200 (Up to XC5210)
Spartan and SpartanXL Devices (All)
Virtex XCV50 |
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FPGA (Standard System Device Support)
XC3x00A/L (All)
XC4000E/X/XL/XLA/XV (All)
XC5200 (All)
Spartan and SpartanXL Devices (All)
Virtex (Up to XCV1000 & XCV1000E) |
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FPGA (Elite System Device Support)
XC3x00A/L (All)
XC4000E/X/XL/XLA/XV (All)
XC5200 (All)
Spartan and SpartanXL Devices (All)
Virtex and Virtex-E (All) |
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*Note:The XC4013L and XC4013XL devices are supported
in the Foundation Series Base System
For more information on the Xilinx Software Solutions, please visit
the Software Solutions Page or contact
your local Xilinx sales office.
More
Information
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