SAN JOSE, Calif., August 9, 1999 – Xilinx, Inc. (NASDAQ:XLNX) today announced the availability of a new Virtex FPGA reference design for a 143 MHz memory controller interface to external ZBT Ô (Zero Bus TurnaroundÔ ) SRAM devices. 

The reference design is ideal for communications and network equipment such as switches and routers that require substantial amounts of memory off the FPGA as well as high bandwidth and no delays between many random and intermixed read and write memory cycles. Synchronous ZBT SRAM memories provide maximum system throughput by using every cycle on the data bus, whereas conventional SRAM devices require additional bus cycles between reads and writes. 

The synthesizable Verilog reference design from Xilinx is for 64K by 36 pipelined and flowthrough ZBT devices, but the design can be easily adapted to create memory controllers for other sized ZBT devices. 

"Virtex devices provide the right mix of system level resources for allowing customers to incorporate state-of-the-art ZBT memories into their designs," said Bruce Weyer, marketing director for the High End FPGA Business Unit at Xilinx. "The Virtex programmable SelectI/O feature supports a variety of signaling standards for off-the-shelf memories, including LVTTL, which is available on most ZBT devices. In addition, the digital delay locked loops on Virtex enable the controller interface to operate at maximum SRAM speeds." 

"Using a Virtex XCV300 FPGA, I was able to meet the design requirement of a 100 MHz, 512K by 32 pipelined ZBT SRAM interface, which is part of our patented Gigabyte CompressionÔ technology," said Winefred Washington, senior hardware engineer at Interactive Silicon, an Austin, Texas, company that licenses intellectual property to semiconductor manufacturers. 

In addition to being able to interface with external memories, Virtex FPGAs also offer both on-chip distributed and block memory resources. Distributed memory is ideal for high speed data processing systems where a small amount of wide memory is needed. Block memory in Virtex FPGAs provides efficient data buffering and temporary storage for processing information found in graphics and networking applications. These memory resources support applications including 125 MHz SDRAM as well. 

"The clock frequency of the SDRAM interface is our major bottleneck in providing higher bandwidth," said Aptitude Vice President and Chief Technical Officer Russell Dietz. "We plan to double the clock frequency on the SDRAM interface to 125 MHz by using Virtex delay lock loops to de-skew the FPGA clock and the SDRAM clock. Another advantage Xilinx Virtex FPGAs offer is their seamless fit into our current ASIC software flow." 

Aptitude, San Jose, California, is using Virtex FPGAs in a high-speed traffic, classification device for tracking performance in networks operating up to OC48 rates. Apptitude develops solutions to monitor applications use and performance on networks. 

The Xilinx ZBT SRAM and SDRAM memory controller reference designs are available without charge from the Xilinx Web site at www.xilinx.com/products/virtex/ref_dsgn.htm. 

In July, Xilinx announced the availability of memory interface cores from third-party AllianceCORE partners that support 125 MHz SDRAM applications. 

Xilinx is the leading innovator of complete programmable logic solutions, including advanced integrated circuits, software design tools, predefined system functions delivered as cores, and unparalleled field engineering support. Founded in 1984 and headquartered in San Jose, Calif., Xilinx invented the field programmable gate array (FPGA) and commands more than half of the world market for these devices today. Xilinx solutions enable customers to reduce significantly the time required to develop products for the computer, peripheral, telecommunications, networking, industrial control, instrumentation, high-reliability/military, and consumer markets. For more information, visit the Xilinx web site at www.xilinx.com. 

Xilinx is a registered trademark of Xilinx Inc. All XC prefixes, AllianceCORE, Virtex and SelectI/O are trademarks of Xilinx, Inc. ZBT and Zero Bus Turnaround are trademarks of IDT Corp. Gigabyte Compression is a trademark of Interactive Silicon. Other brands or product names are trademarks or registered trademarks of their respective owners. 
#9944 
 

Editorial Contact:	Product Marketing Contact:
Mike Seither	Amy Hills
Xilinx, Inc.	Xilinx, Inc.
(408) 879-6557	408-879-6835
mike.seither@xilinx.com	amy.hills@xilinx.com