Virtex Series FPGAs - Reference Designs

Virtex Series FPGAs Reference Designs

Xilinx offers a number of reference designs in the form of application notes with supporting design files. These designs represent good starting points for implementing simple to complex functions in Xilinx programmable logic.

These designs are supplied free from Xilinx, and come without technical support or warranty. For pre-implemented and verified functions that include technical support, we suggest that you consider the Xilinx LogiCORE or AllianceCORE products.

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Reference Design License Agreement. All Reference Designs found on the Xilinx Website are bound by this agreement. These designs are supplied free from Xilinx, and come without technical support or warranty.

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Reference Designs

Multi-channel 622 MHz LVDS Data Transfer with Virtex-E Devices	Reference Design	Application Note XAPP233
Create a high-speed LVDS receiver and transmitter on a single Virtex-E FPGA suitable for point-to-point data transmission at a data rate of 622 Mb/s.

IDCT Implementation Virtex Devices for MPEG Applications	Reference Design	Application Note XAPP208
Synthesizable Verilog code reference design.

Data-Width Conversion FIFOs using Virtex Block SelectRAM	Reference Design	Application Note XAPP205
The dedicated blocks of true, dual-port, synchronous RAM in the Virtex family are used to create effective data-width conversion FIFOs.

CAM in Block Select RAM	Reference Design	Application Note XAPP204
The reference design demonstrates a complete solution including an encoded address output, a match flag, and in addition to fast read access, a fast 2- clock-cycle erase/write access.

Designing Flexible, Fast CAMs with Virtex Slices	Reference Design	Application Note XAPP203
The reference design proposes an address encoder and match flag generation in gates or in 3-state buffers. These options are open to the designer according to the final CAM implementation.

CAM in ATM Applications	Reference Design	Application Note XAPP202
A hierarchical, synthesizable design implementing a search engine or CAM in Virtex slices.

Using the Virtex Delay-Locked Loop	Reference Design	Application Note XAPP132
VHDL and Verilog reference design.

1.6 Gbytes/s DDR SDRAM Controller	PC: 64-bit UNIX: 64-bit PC:16-bit UNIX: 16-bit	Application Note XAPP200
These reference designs demonstrate the use of the CLKDLL, the shift register LUTs, and the SelectI/O™ in Virtex FPGAs to interface with external DDR SDRAMs at 100MHz (1.6 Gbytes/s). The 64-bit and 16-bit designs are developed using both Verilog/VHDL, and are easily modified for different system design requirements.

200 MHz ZBT SRAM Interface	Verilog Design VHDL Design	Application Note XAPP136
A synthesizable, auto-place-and-route 200 MHz ZBT SRAM interface in the Virtex FPGA. Interfaces for both pipelined and flow-through are provided along with the appnote.

SDRAM Controller	VHDL Design Verilog Design	Application Note XAPP134
A synthesizable, parameterizable, flexible, auto-placed-and-routed synchronous DRAM controller in the Virtex FPGA family. A 32-bit wide data interace version can run up to 125 MHz when automatically placed and routed in a Virtex -6 speed grade. Hand placed versions of the design can run even faster.

170MHz FIFOs	Reference Design	Application Note XAPP131
512x8 Asynchronous (independent clock) and synchronous (common clock) block RAM based FIFOs for Virtex written in Verilog and VHDL. 170 MHz performance possible in a Virtex -6 speed grade device. Also included is a parameterizable version of a VHDL Asynchronous FIFO for Virtex with associated testbench files.

Configuring Virtex FPGAs from Parallel EPROMs with a CPLD	Reference Design	Application Note XAPP137
Simple interface design to configure a Virtex device from a parallel EPROM using the SelectMAP configuration mode.

Partial Reconfiguration	Reference Design	Application Note XAPP153
Reference design and appnote on Semaphore registers, which involves an external host performing read/write operations using partial reconfiguration through the Virtex configuration port while the rest of the circuit is still in operation.

Coefficient Multiplier (KCM) Generator	Reference Design	Application Note
Constant Coefficient Multiplier (KCM) generator for Virtex. This DOS utility generates RPM based cores for KCM multipliers. Supports 8, 12, 16 and 20 bit data, signed/unsigned, and combinatorial/pipelined modules.

Library of 19 Virtex Multipliers	Reference Design	Application Note
Library of 19 Virtex variable by variable multipliers. Includes signed or unsigned, combinatorial or pipelined point solutions, RPMed and optimized for speed and area.

Parameterizable Distributed RAM for Virtex (VHDL)	Reference Design	Application Note
Parameterizable VHDL RAMs for Virtex - Use SelectRAM(TM) for more efficient storage - Support memory depths from 64 to 8192 in 16 bit increments - Source files for Single Port / Dual Port versions - Selectable registered inputs/outputs - Selectable input/output clock enables - Selectable multiplexing scheme for combining RAM primitives Supports Synopsys FPGA Express and Synplicity synthesizers.

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