Multi-channel 622 MHz LVDS Data Transfer with Virtex-E Devices |
Reference
Design![Internet Link Internet Link](../rphttp01/portal.gif) ![](../rp00001/rp0019b.gif) |
Application Note XAPP233 |
Create a high-speed LVDS receiver and transmitter on
a single Virtex-E FPGA suitable for point-to-point data transmission
at a data rate of 622 Mb/s. |
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IDCT Implementation Virtex Devices for MPEG Applications |
Reference
Design![Internet Link Internet Link](../rphttp01/portal.gif) |
Application Note XAPP208 |
Synthesizable Verilog code reference design. |
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Data-Width Conversion FIFOs using Virtex Block SelectRAM |
Reference
Design![Internet Link Internet Link](../rphttp01/portal.gif) |
Application Note
XAPP205 |
The dedicated blocks of true, dual-port, synchronous
RAM in the Virtex family are used to create effective data-width conversion
FIFOs. |
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CAM in Block Select RAM |
Reference
Design![Internet Link Internet Link](../rphttp01/portal.gif) |
Application Note XAPP204 |
The reference design demonstrates a complete solution
including an encoded address output, a match flag, and in addition
to fast read access, a fast 2- clock-cycle erase/write access. |
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Designing Flexible, Fast CAMs with Virtex Slices |
Reference
Design![Internet Link Internet Link](../rphttp01/portal.gif) |
Application Note XAPP203 |
The reference design proposes an address encoder and
match flag generation in gates or in 3-state buffers. These options
are open to the designer according to the final CAM implementation. |
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CAM in ATM Applications |
Reference
Design![Internet Link Internet Link](../rphttp01/portal.gif) |
Application Note
XAPP202
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A hierarchical, synthesizable design implementing a
search engine or CAM in Virtex slices. |
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Using the Virtex Delay-Locked Loop |
Reference
Design![Internet Link Internet Link](../rphttp01/portal.gif) |
Application Note XAPP132 |
VHDL and Verilog reference design. |
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1.6 Gbytes/s DDR SDRAM Controller |
PC:
64-bit ![Internet Link Internet Link](../rphttp01/portal.gif)
UNIX:
64-bit ![Internet Link Internet Link](../rphttp01/portal.gif)
PC:16-bit ![Internet Link Internet Link](../rphttp01/portal.gif)
UNIX:
16-bit![Internet Link Internet Link](../rphttp01/portal.gif)
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Application Note
XAPP200 |
These reference designs demonstrate the use of the CLKDLL,
the shift register LUTs, and the SelectI/O™ in Virtex FPGAs to interface
with external DDR SDRAMs at 100MHz (1.6 Gbytes/s). The 64-bit and
16-bit designs are developed using both Verilog/VHDL, and are easily
modified for different system design requirements. |
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200 MHz ZBT SRAM Interface |
Verilog
Design
VHDL
Design ![Internet Link Internet Link](../rphttp01/portal.gif)
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Application Note
XAPP136 |
A synthesizable, auto-place-and-route 200 MHz ZBT SRAM
interface in the Virtex FPGA. Interfaces for both pipelined
and flow-through are provided along with the appnote. |
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SDRAM Controller |
VHDL
Design
Verilog
Design |
Application Note XAPP134 |
A synthesizable, parameterizable, flexible, auto-placed-and-routed
synchronous DRAM controller in the Virtex FPGA family. A 32-bit wide
data interace version can run up to 125 MHz when automatically placed
and routed in a Virtex -6 speed grade. Hand placed versions of the
design can run even faster. |
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170MHz FIFOs |
Reference
Design![Internet Link Internet Link](../rphttp01/portal.gif) |
Application Note XAPP131 |
512x8 Asynchronous (independent clock) and synchronous
(common clock) block RAM based FIFOs for Virtex written in Verilog
and VHDL. 170 MHz performance possible in a Virtex -6 speed grade
device.
Also included is a *parameterizable* version of a VHDL Asynchronous
FIFO for Virtex with associated testbench files.
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Configuring Virtex FPGAs from Parallel EPROMs with a CPLD |
Reference
Design
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Application Note XAPP137
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Simple interface design to configure a Virtex device
from a parallel EPROM using the SelectMAP configuration mode. |
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Partial Reconfiguration |
Reference
Design![Internet Link Internet Link](../rphttp01/portal.gif) |
Application Note XAPP153 |
Reference design and appnote on Semaphore registers,
which involves an external host performing read/write operations using
partial reconfiguration through the Virtex configuration port while
the rest of the circuit is still in operation. |
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Coefficient Multiplier (KCM) Generator |
Reference
Design |
Application
Note |
Constant Coefficient Multiplier (KCM) generator for
Virtex. This DOS utility generates RPM based cores for KCM multipliers.
Supports 8, 12, 16 and 20 bit data, signed/unsigned, and combinatorial/pipelined
modules. |
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Library of 19 Virtex Multipliers |
Reference
Design |
Application
Note |
Library of 19 Virtex variable by variable multipliers.
Includes signed or unsigned, combinatorial or pipelined point solutions,
RPMed and optimized for speed and area. |
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Parameterizable Distributed RAM for Virtex (VHDL) |
Reference
Design |
Application
Note |
Parameterizable VHDL RAMs for Virtex
- Use SelectRAM(TM) for more efficient storage
- Support memory depths from 64 to 8192 in 16 bit increments
- Source files for Single Port / Dual Port versions
- Selectable registered inputs/outputs
- Selectable input/output clock enables
- Selectable multiplexing scheme for combining RAM primitives
Supports Synopsys FPGA Express and Synplicity synthesizers.
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