Timing Analysis

Title	Size
XAPP174: Using Delay-Locked Loops in Spartan-II FPGAs	120 KB
XAPP166: TAU/BLAST Support in 2.1i	20 KB
XAPP132: Using the Virtex Delay-Locked Loop	90 KB
XAPP111: Using the XC9500XL Timing Model	100 KB
XAPP115: Planning for High Speed XC9500XL Designs	110 KB
XAPP095: Set-up and Hold Times	10 KB
XAPP071: Using the XC9500 Timing Model	60 KB
XAPP094: Metastable Recovery (FPGAs)	20 KB
XAPP077: Metastability Considerations (CPLDs)	30 KB
XAPP302: Metastability Characteristics for Philips CPLDs	40 KB
XAPP096: Overshoot and Undershoot	10 KB
XAPP018: Estimating the Performance of XC4000E Adders and Counters	40 KB
XAPP045: XC4000 Series Technical Information (Capacitive Loading, Ground Bounce)	30 KB

Title	Size
XBRF015: Speed Metrics for High Performance FPGAs	100 KB
XBRF006: PLL Design Techniques and Usage in FPGA Design	40 KB

Title	Issue
Two Simple Solutions For Tricky Problems	Q4 '99
Unusual Clock Dividers	Q3 '99
FlibGen, FlibTime, and ChipView - Power Tools for FPGA Design	Q3 '99
FPGA-on-Board Timing Verification Using Tau	Q3 '99
The Increasing Importance of HDL Verification	Q2 '99
Determining Clock Skew When the Virtex DLL Drives Multiple Copies of a Clock Off Chip	Q2 '99
1 GHz Performance Milestone - 0.18m, 1.8V FPGA	Q1 '99
Frequency Synthesis Techniques	Q1 '99
Heat Gun and Cold Spray - Your Best Debugging Tools	Q4 '98
New Spartan -4 Devices for High Speed Applications	Q3 '98
Q&A: How Can I Use the "Clock Enable Pin" Instead of Gated Clocks in My HDL Designs?	Q3 '98
Printed Circuit Board Design Considerations	Q2 '98
Self Initiated Global Reset	Q2 '98
CMOS I/O Characteristics	Q2 '98
Low Power FPGA Achieves 400 MHz Performance	Q2 '98
Using IBIS Specifications	Q1 '98
A 200 MHz Pulse Generator	Q1 '98
An Innovative Way to Reduce Electromagnetic Interference	Q1 '98
Trouble-Free Switching Between Clocks	Q1 '97
A Look at Minimum Delays	Q2 '96
Metastability Recovery in Xilinx FPGAs	Q3 '96
Using Decoupling Capacitors	Q1 '96
Synchronous RAM Timing in the XC4000E FPGA	Q4 '95
User Defined Schmitt Triggers	Q4 '95
Low Pass Filtering of Noisy Inputs	Q3 '95