The Industry's First General-Purpose 64-bit, 66 MHz PCI Solution |
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The Virtex and Virtex-E FPGA families meet demand for compliance, flexibility, and performance with 66 MHz PCI -- before the availability of standard chips, ASICs and specialized FPGAs.
New 64/66 PCI LogiCORE product for Virtex and Virtex-E FPGAs |
The Real 64/66 PCI from Xilinx enables designers to implement a 64-bit, 66 MHz PCI
interface in a standard Virtex or Virtex-E FPGA, fully compliant to the PCI specification
V2.2, supporting a sustained throughput of 528 Mbytes/second. In an XCV300 or XCV300E FPGA the PCI cores occupy 12% of the resources, which leaves over 260,000 system gates for the designer to add dual-port customized FIFOs, DMA controller, and other custom logic functions. In an XCV1000 or XCV1000E the cores occupy only 3% of the FPGA. |
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Key Features | |
Real Availability - Cores and the devices are available today Real Compliance - Timing is guaranteed by Smart-IP technology |
Real Flexibility - Targeted to Xilinx standard Virtex FPGAs Real Performance - Zero wait-state burst and 64-bit back-end interface |
Real Availability The 64/66 PCI LogiCORE design is available for Virtex and Virtex-E devices. All Virtex and several Virtex-E devices are available today. See datasheet for specific devices and packages. Since September 1998, more than a dozen beta customers have already been using the Real 64/66 PCI in applications such as Gigabit Ethernet, ATM and Fiber Channel adapters, DSP/Imaging boards, disk drive arrays and high-end printer interfaces. Beta customers include Ascend Communications, Dome Imaging, and Kodak. |
The Dome Imaging MX2/PCI board is the first in a new family of high resolution display controllers for the medical imaging market that can handle transfers of over 500 MB/s from the host. |
"With the Real 64/66 PCI products from Xilinx, we were able to implement a fully compliant PCI interface - plus other functions such as direct memory access (DMA), 4 dual-port FIFOs, and 200,000 gates of our own unique design - in a single device," said John Beck, Principal Engineer from DOME Imaging, Inc. "After evaluating different solutions in the market, we found that only Xilinx could meet the demanding requirements for full 66 MHz PCI compliance." |
Real ComplianceThe Real 64/66 PCI solution provides full protocol, timing and electrical PCI v2.2 compliance. Thanks to the fast multi-standard SelectI/OTM interfaces in a Virtex FPGA, a single I/O buffer per PCI signal can be used, which is required to meet the PCI specification. The Real 64/66 PCI core is based on the already proven 32-bit PCI solution from Xilinx that to date has been used in more than 1,000 customer designs. It is verified with Xilinx internal testbench that simulates over 6 million PCI cycles, which ensures a high-quality PCI product. To minimize customers' development time, The Real 64/66 PCI core guarantees all the critical PCI timing. We achieve this by characterizing the Virtex silicon together with the LogiCORE PCI design and then applying strict implementation constraints. As a result, the implementation of the most critical parts of the PCI core looks exactly the same every time the core is compiled, independent of the tools that are used and independent of the customers' unique back-end design. We call this method of guaranteeing the timing with maintained flexibility Smart-IP technology and it is only available from Xilinx. The guarantee includes the extremely challenging 3ns maximum setup time, 2ns minimum clock-to-out, and 0ns hold time of the Critical Path shown in the figure below. The Critical Path becomes the constraint when decoding the Initiator Ready (IRDY) and Target Ready (TRDY) signals, which must be completed at full speed in an Initiator interface bursting data without wait-states. The Critical Path |
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Real FlexibilityThe Real 64/66 PCI from Xilinx is a firm core targeted to our standard off-the-shelf Virtex and Virtex-E FPGA families. Because the PCI interface is implemented in a standard FPGA and not a specialized FPGA with an embedded PCI interface, you will benefit from unparalleled flexibility, still with guaranteed 66MHz PCI timing. There are several benefits of this methodology
PCI Design Files Over the Internet |
As part of Xilinx Silicon Xpresso initiative, all LogiCORE PCI design files are distributed over the Internet and are available in the Xilinx PCI Lounge, a password protected area on this website. LogiCORE PCI V3.0, Configuration and Download (Demo Version) The download procedure couldn't be simpler:
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The PCI design is Supported with the Following Design Tools |
Design Entry:
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Design Verification:
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Real Performance The Real 64/66 PCI from Xilinx offers up to the maximum sustained throughput of 528 Mbytes per second. This is achieved by:
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PCI TrainingTo further complete the Xilinx PCI solution, Xilinx offers a three-day PCI course for customers who are planning PCI systems. The course will give an introduction to the PCI standard, cover configuration and integration of core, system integration, verification and debug. XPERTS Design ServicesTo support your PCI design you have worldwide access to certified PCI experts that can provide design services including:
More Information |
Press Release | Searching
the Ideal Core for FPGAs article on pros and cons of soft vs. embedded cores |
LogiCORE PCI64/66 Data Sheet | Other PCI solutions from Xilinx |
Virtex 2.5V FPGAs Series Data Sheet | Xilinx Sales Offices |
Questions and Answers |