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AllianceCORE Partner-CSELT logo

CSELT S.p.A

AllianceCORE
Partner Profile


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[] Overview
[] AllianceCORE Products
[] Areas of Technical Expertise
[]Contact CSELT

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[] IP Center
[] Core Solutions - What's New

Overview

CSELT S.p.A is the Telecom Italia Group company for study, research, experimentation, and qualification in the field of telecommunications and information technology.
CSELT provides a synthesizable Soft IP library - the VIP libraryTM - consisting of customizable system level cores for designing complex applications with a new design approach oriented to fast and safe prototyping. VIP libraryTM is the answer to all Information and Communication Technologies (ICT) product requirements: system knowledge, technological expertise and time to market. The library includes cores commonly used in ASICs and FPGAs for Fast Packet Switching (ATM, TCP/IP), Video and Wireless systems. Cores are available in netlist format and in source code (VHDL) format. Netlists are released with customized simulation test benches, while source code is released with hierarchical synthesis scripts and high level programmable simulation test benches.

The VIP LibraryTM has been used to realize a variety of ICs and systems for ATM switching and access nodes, Optical Network Units, ATM Virtual Private Network servers, and switched Digital Video Broadcast equipment.

CSELT's products and services also include:

  • Hard macro library: a high performance hard macro IP library including low power memories, differential low swing pads, PLLs, phase aligners, embedded
  • Content Addressable Memories
  • Support and user training courses
  • IP design methodology courses

AllianceCORE Products

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The AllianceCORE Products Table shows AllianceCORE products available from CSELT. Adobe Acrobat versions of the datasheets for these can be downloaded from the table. Contact CSELT S.p.A for pricing. 


AllianceCORE Products Table

Product Functional Description
Asynchronous Transfer Mode
Distributed Sample Scrambler New Distributed Sample Scrambler for cell-based data transmission (example, ATM).
Distributed Sample Descrambler New Distributed Sample Descrambler for cell-based data transmission (example, ATM).
UTOPIA_Level 2_Transmitter New Utopia level 2 slave interface. Implements transmitter mode; protocol conversion from UTOPIA level 2, PHY side to Pb.
UTOPIA_Level 2_Receiver New Utopia level 2 slave interface. Implements receiver mode; protocol conversion from Pb to UTOPIA level 2, PHY side.
Standard Bus Interface
Arbiter New Controls the access of Units to a shared resource (example, a bus)
Telecommunications
Noisy Transmission Channel Model New Model of a noisy transmission channel with customizable and programmable noise distribution.
Forward Error Correction
Convolutional_Encoder New Parametric convolutional encoder.
Viterbi_DecoderNew Parametric Viterbi decoder.

Areas of Technical Expertise

The following table of products demonstrates CSELT's areas of technical expertise. Xilinx and CSELT are in the process of evaluating these products to determine which ones are suitable as AllianceCORE products. If you have a need for a specific product then contact CSELT for information or availability. 

Product Functional Description Gates
Communications & Networking
ATMGEN ATM cell generator. UTOPIA level 1 and RACE Pb supported.  
ATM_3PRAM ATM triple port RAM with FIFO access for ATM streams. 45,0001
ATMALIGN HEC based identification of ATM cell boundaries as specified in the TIU-T I.432Recommendation. 30001
FIPO First in priority out cell real time sorter based on a fast partial ordering algorith for ATM traffic shaping and spacing. 20,0001
FSS Frame Synchronous Scrambler cell performs line coding and decoding of data frames. 15,0001
IPCAM Internet Protocol Content Addressable Memory (CAM) for fast and flexible search in the forwarding Internet Protocol tables. 50001
IP_GEN Internet Protocol cell generator.  
MPEG_GEN MPEG packet generator. 8-bit MPEG cell transmission.  
SDHALIGN SDH Frame delineation based on a programmable synchronization sequence. 20001
SOFTCAM Virtual Content Addressable Memory compresses an input identifier into a smaller output identifier (like bit strings in ILI, VPI, VCI, and PTI values in ATM cell header). 30001
UPARCO/DPARCO Upward/downward parallelism conversion of a data stream. 10001
UTOPIA_L1 UTOPIA level 1 interface; PHY side, transmitter and receiver mode cells. Protocol conversion between UTOPIA and Pb. 20001
VERCOR CRC based error detection and correction on selected fields of each data block in ATM cell streams. 10,0001
VQE Virtual Queuing Engine to perform push or pop operations of data (ATM cells) on a logic queue. 15,0001
Base-level Functions
MC68K Bus functional model of the MC68000 processor.  
MPI Generic microprocessor bus protocol. 20,0001
SDRAM_SGEN SDRAM signal generator handles the access protocol to an external 16 Mbit SDRAM. 20001
SRAM_INT SRAM interface manages access to an external static RAM. 30,0001
DSP Functions
FIDCT Forward Inverse Discrete Cosine Transform. Multiplexed Forward/Inverse DCT functionality. 40,0001
RS_DECODER Reed Solomon decoder. 40,0001
RS_ENCODER Reed Solomon encoder. 10001
Note:
1. All gate counts are for example implementations and are application dependent.

Contact CSELT

Via G. Reiss Romoli, 274
I-10148 Torino
ITALY
Phone: +39 011 228 7165
Fax: +39 011 228 7003
E-mail:viplibrary@cselt.it
URL: www.cselt.itInternet Link

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