Answers Database
NGDBUILD 1.4: "ERROR:basnb:79 - Pin mismatch between block ..." with Synplify 5.x
Record #4891
Product Family: Software
Product Line: FPGA Implementation
Product Part: ngdbuild
Product Version: 1.4
Problem Title:
NGDBUILD 1.4: "ERROR:basnb:79 - Pin mismatch between block ..." with Synplify 5.x
Problem Description:
Urgency: Standard
General Description: Using M1.4 together with Synplify 5.x and
Coregen or Logiblox, Ngdbuild will error with this type of message:
ERROR:basnb:79 - Pin mismatch between block "XCOUNTER", TYPE="tenths",
and file "/home/paulo/3rd/synplicity/verilog/watch/par/tenths.ngo"
at pin "Q_OUT[9:0](0)". Please make sure that all pins on the
instantiated component match pins in the lower-level design block.
(Pin-name matching is case-insensitive.)
The problem is that CoreGen writes out the pin names to its EDIF
netlist as individual bits, and EDIF2NGD is unable to correlate the
individual bits in the CoreGen EDIF netlist with the bus name reference
in the Synplify netlist. EDIF2NGD 1.5 handles embedded ranged
strings in array names. Please see (Xilinx Solution 5416).
Solution 1:
Use M1.5 to work around the problem. M1.5 edif2ngd recognizes
the following syntax:
(port (array (rename tenthsout "TENTHSOUT[9:0]") 10) (direction OUTPUT))
and splits the bus accordingly into 10 scalar bits. However,
pre-M1.5 versions of edif2ngd assume that the signal,
"TENTHSOUT[9:0]", is 1-bit wide instead of a vector.
Xilinx recommends using the Synplicity XNF flow for 1.4, and
the EDIF flow for 1.5. The XNF format can be selected from the
Synplify menu as follows:
"Target -> Set device options -> Result format -> xnf"
Please see (Xilinx Solution 4272) for details on other
potential pin-mismatch issues with Synplify 5.x.
Solution 2:
The user can specify to have his bus ports expanded to bits with
the syn_noarrayports attribute within Synplify. Please see
(Xilinx Solution 504). Also, within Coregen or Logiblox, select
the bus-notation as "[]". Please read (Xilinx Solution 4041) for
a description of generating CorGen modules.
End of Record #4891 - Last Modified: 03/09/99 15:14 |
