Answers Database V2.1i COREGEN, C_IP2: Known Issues in the C_IP2 IP Update Record #7395 Product Family: Software Product Line: LogiCore Product Part: Coregen IP Modules Problem Title: V2.1i COREGEN, C_IP2: Known Issues in the C_IP2 IP Update Problem Description: Urgency: hot General Description: C_IP2 IP Update Known Issues Solution 1: VHDL Simulation Analyze Order: (Xilinx Solution #6250) has been updated to indicate the order in which the VHDL behavioral simulation models must be analyzed for this release. Known Issues 1. (Xilinx Solution #7409) V2.1i COREGEN, FOUNDATION: Optional pins which are not requested still appear on the Foundation symbol for a CORE Generator Core 2. (Xilinx Solution #6853) - V2.1i COREGEN, F2.1i FOUNDATION, NGDBUILD: Unexpanded block error -- ... because one or more pins on the block ... were not found 3. (Xilinx Solution #7391) - C_IP2, V2.1i COREGEN: Virtex Variable Parallel Multiplier "Set Overrides Clear" option behaves the same way as "Clear Overrides Set" 4. ((Xilinx Solution #7393) - C_IP2, V2.1i COREGEN: Virtex Variable Parallel Multiplier module latency does not match the 4K (XC4000) version of the core 5. (Xilinx Solution #7396) - C_IP2, V2.1i COREGEN: Virtex Variable Parallel Multiplier "Combinatorial" and "Pipelined Registers" option interaction 6. (Xilinx Solution #7441) - V2.1i COREGEN, C_IP2: "ERROR: Unable to find   library for core Sine-Cosine_Look-Up_Table|xilinx|xc4000_all" Also, the known issues documented for the C_IP1 release still apply, as documented in (Xilinx Solution #7149). End of Record #7395 - Last Modified: 10/20/99 11:39

For the latest news, design tips, and patch information on the Xilinx design environment, check out the Technical Tips!