| A thru H |
Definition of Terms 
|
| Asynchronous Logic |
Logic that changes independently of clock. |
| Automatic Power Down Mode |
The device can be brought into this mode by selectively controlling
the features of a design which consume large amounts of power. The reduction
in power is obtained without clearing the registers. As a result, the register
data is retained. The inputs and outputs are not disabled and as a result,
the device remains active during this mode. |
| Bitstream (Bitmap) |
The bitstream is a binary representation of an implemented FPGA design.
The bit-stream is generated by the Xilinx software tool ‘BITGen’ and the
output file has <.bit> file extension. |
| Configuration |
It is the process of loading design-specific bitstreams into one or
more FPGA devices to define the functional operation of the logical blocks,
their interconnections, and the chip I/O. |
| Configuration Mode Control |
SpartanXL devices have three configuration modes: Slave Serial, Master
Serial and Express Mode. These modes are selected by the M1 and M0 pins
on the device. In addition, the devices can be configured through boundary
scan logic. |
| Dynamic Current |
It is the amount of current the device needs when it is active. The
dynamic current is mainly due to switching of internal nodes, loading on
the outputs and external clocks. |
Glitch
|
A situation where the outputs of a source device go active while the
inputs of a target device are receptive to signal transitions. Here, it
is possible for the outputs of a source device to go from a high impedance
state to High or Low logic level, to cross the switching threshold of the
inputs to the target device thereby causing a false transition. |
| I thru P |
|
| Manual Power Down Mode |
This mode is activated manually by using the PWRDWN pin. The device
remains in standby mode as long as the PWRDWN pin stays Low. Configuration
data (bitmap) is retained and registered data is lost. |
| Performance |
For registered designs, it is the system clock frequency at which the
design can function. For combinatorial designs, it is the pin-to-pin delay. |
| Power |
It is the amount of electrical energy consumed by the device for its
operation. |
| Power Down Mode |
Here, the device goes into low power mode consuming minimal amount
of current. Excellent for long periods of inactivity or minimal activity. |
| Power Down Time |
It is the time required by the device to go from the normal operating
mode to the Power Down Mode. |
| Pull-Down |
Resistor connected between an IO pin and GND to pull the unused pin
to logic Low to prevent it from floating. |
| Pull-Up |
Resistor connected between an IO pin and VCC to pull the unused pin
to logic High to prevent it from floating. |
| Q thru Z |
|
| Static Current |
It is the amount of current needed by an inactive device connected
to the power supply. |
| Static State or DC State |
In this state, there is no signal activity within the device. The inputs
and outputs are not transitioning and the power required is only due to
static current. |
| Synchronous Logic |
It is the logic that changes with the clock. |
| Transformer |
It is the device used to change the voltage levels. Example: Device
taking 220 Volts as Input and stepping down to 110 Volts as Output. |
| Utilization |
It is the amount of resources used in the device. The resources are:
logic cells, IO cells, flip-flops and interconnect. |
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