Communications Benchmarks

1024-point, 16-bit complex FFT

• 10 microsecond transform time
• Single device solution in the largest Virtex device
• Datapath and all data storage on-chip

Heterodyne + 20:1 polyphase decimating FIR

• 20 polyphase arms, 24 taps per arm
• 8-bits I-Q data, 8-bit coefficients
• 28,800 Million MACs in actual design
• Single device solution in the largest Virtex device
• Includes Heterodyne, Direct Digital Synthesizer and Complex Polyphase Decimator

Here are examples of FPGA communications performance benchmarks.

A complex FFT with 16 bit data is capable of continuous transforms at a 10 usec rate. This self contained single chip solution fits in a single FPGA device without the need for any external memory buffers.

A single FPGA can implement a complete receiver heterodyne function requiring over 28,000 million (28 Billion) multiply accumulate operations per second. Note that this function will only use up one fourth the resources that are available on the board we just described.