The Configuration Problem Solver
Related Solution Records
FPGA should be active.
Solution 2748: "FPGA Configuration: All I/O (including D/P) Tristate during configuration."
Solution 2427: "Hardware Debugger: Polarity of Reset signal is active Low."
Solution 134: "FPGA Configuration: Effect of power-glitch invoked reset on xc2000/3000..."
HISTORY
Family:
XC3000
Mode:
Master Serial
D/P:
HIGH
LDC:
LOW
CCLK:
STOP
