The Forge Suite of Hardware Development Tools

The suite compiles high level software language code into efficient Verilog-HDL files compatible with industry-standard RTL synthesis and simulation tools.

Through advanced analysis and optimization techniques, the compiler automates low-level detailed design, creating efficient hardware architectures from functional software descriptions while remaining compatible with existing tool investments.

Instead of stopping at gate-level synthesis, the Forge provides the ability to synthesize multiple architectural constructs from a single functional specification. Our advanced algorithms allow Forge to read functional high level code and infer optimized architectures which meet design specifications for function and performance.

The Verilog-HDL output is highly structured and conveys the key architectural and logic latency details required for efficient low-level implementation.

In this way, Xilinx's solutions offer a new level of productivity without the disruption of a wholesale change in current EDA design processes. The order-of-magnitude productivity improvement demonstrated by the Forge gives companies the power to handle the complexity of modern designs while at the same time get to market faster. Moreover, for the first time, Xilinx software allows software engineers to enter the IC design process, broadening the range of potential designers and addressing the acute shortage of IC engineers.