What's New on The Virtex Web Site

What's New Overview: General Overview Virtex/Virtex-E           Virtex-EM Virtex-II Architecture Device Families: Virtex Virtex-E Virtex-EM                   Tech Topics  Datasheets  App Notes/Ref Designs  Configuration  Signal Integrity  Demo Boards Design Utilities: Chipscope ILA Power Estimator SelectLink Tool WebACE ZBT SRAM Calculator  More Information

New Application Notes and Reference Designs   Data to Clock Phase Alignment Data Recovery Transposed Form FIR Filters New Press Releases Xilinx Establishes Leadership Direction for High-Bandwidth I/O Technologies Xilinx and Conexant Announce Licensing Agreement of SkyRail 3.123 Gbps CMOS Serial Transceiver Technology Xilinx First to Ship Production Release of POS-PHY Level 3 Cores Xilinx Acquires Formal Verification Technology Virtex-II Architectural Preview

Material pertains to all Virtex series devices unless specifically noted in parentheses.

to view the  PDF files below. 

Application Notes & Reference Designs

Title Version Size Reference Design Date XAPP225: Data to Clock Phase Alignment 1.0 48K Reference Design 9/18/00 XAPP224: Data Recovery 1.0 43K Reference Design 7/26/00 XAPP219: Transposed Form FIR Filters 1.0 1806K PC: VHDL UNIX: VHDL 7/26/00

Press Releases