CoolRunner: Tips and Techniques   Design Entry Tools Hardware/Programming Fitting Tools Reference and Architecture

Design Entry Tools

• Xilinx Answer #7523 : XPLA Professional: Implementing a latch in a CoolRunner?
• Xilinx Answer #7545 : XPLA Professional: Simultaneous reset and preset.
• Xilinx Answer #7516 : XPLA Professional: Using Control Files with the Coolrunner Product
• XAPP312: Differences In ABEL and PHDL
• XAPP316: Xilinx Project Navigator XST - XPLA Professional Design  Flow

Implementation Fitting Tools

• Xilinx Answer #7504 : CoolRunner XPLA Professional: Design does not fit
• Xilinx Answer #7543 : XPLA Professional: Pin reassignment.
• XAPP313: Achieving High Performance in a CoolRunnerTM XCR3960

Reference and Architecture

• Xilinx Answer #7604 : XPLA Architecture: CoolRunners and internal weak pull-up resistors.
• Xilinx Answer #7631 : XPLA1: Number of macrocells in a logic block and presence of a PAL and PLA.
• Xilinx Answer #7639 : XPLA1: Hysterisis on inputs or clock pins.
• Xilinx Answer #7643 : XPLA1: Can the XPLA1 implement asynchronous clocks?
• Xilinx Answer #7651 : XPLA2: Are the XPLA2 devices SRAM-based or EEPROM-based?
• XAPP315: Implementing an I2C Bus Controller in a CoolRunnerTM CPLD
• XAPP328: Design of a MP3 Portable Player using a CoolRunner CPLD
• XAPP310: Power Up Reset Characteristics of CoolRunner CPLDS

Hardware/Programming Solutions

• Xilinx Answer #7566 : XPLA PC-ISP Programmer: How to load a JEDEC file, versus a JCD file?
• Xilinx Answer #7568 : XPLA PC-ISP Programmer: Programmer cannot find or recognize a file
• Xilinx Answer #7565 : XPLA PC-ISP Programmer: Generating ATE vectors.
• Xilinx Answer #7571 : XPLA PC-ISP Programmer: Accessing non-CoolRunner devices.
• Xilinx Answer #7577 : XPLA PC-ISP Programmer: Generating binary files for JEDEC programming.
• Xilinx Answer #7652 : XPLA2: Configuration modes of the XPLA2 devices.
• Xilinx Answer #7587 : XPLA PC-ISP Programmer: Which download cable is needed
• Xilinx Answer #7576 : XPLA PC-ISP Programmer: Generating vectors for Microcontroller use.
• Xilinx Answer #7574 : XPLA PC-ISP Programmer: New parts do not program via ISP in a known good system.
• Xilinx Answer #7642 : XPLA1: What is the active signal polarity for Reset / Preset / Output Enable / Global Tri-State?
• XAPP307: Terminating Unused CoolRunner I/O Pins
• XAPP300: In-System programming (ISP)
• XAPP302: Metastability Characteristics for Philips CPLDs