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Using Tau and Xilinx for board level timing analysis. The App note can be
downloaded from here
Xilinx is supporting Mentor C.2 with Xilinx 2.1i. In order for
Co-simulation (schematic and VHDL) to work you must have
the latest Mentor C.2 patches available and Model Technology
ModelSim 5.2d must be used.
For information on Mentor Graphics, visit the Mentor Graphics Home Page.
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